Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Ingenic SoCs TCU IRQ driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mfd/ingenic-tcu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/overflow.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <dt-bindings/clock/ingenic,tcu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static DEFINE_PER_CPU(call_single_data_t, ingenic_cevt_csd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) struct ingenic_soc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) struct ingenic_tcu_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	unsigned int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct clock_event_device cevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	char name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) struct ingenic_tcu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct clk *cs_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	unsigned int cs_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct clocksource cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned long pwm_channels_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct ingenic_tcu_timer timers[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static struct ingenic_tcu *ingenic_tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static u64 notrace ingenic_tcu_timer_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct ingenic_tcu *tcu = ingenic_tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	regmap_read(tcu->map, TCU_REG_TCNTc(tcu->cs_channel), &count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static u64 notrace ingenic_tcu_timer_cs_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	return ingenic_tcu_timer_read();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static inline struct ingenic_tcu *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) to_ingenic_tcu(struct ingenic_tcu_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	return container_of(timer, struct ingenic_tcu, timers[timer->cpu]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static inline struct ingenic_tcu_timer *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) to_ingenic_tcu_timer(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return container_of(evt, struct ingenic_tcu_timer, cevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static int ingenic_tcu_cevt_set_state_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct ingenic_tcu_timer *timer = to_ingenic_tcu_timer(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct ingenic_tcu *tcu = to_ingenic_tcu(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	regmap_write(tcu->map, TCU_REG_TECR, BIT(timer->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static int ingenic_tcu_cevt_set_next(unsigned long next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				     struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct ingenic_tcu_timer *timer = to_ingenic_tcu_timer(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct ingenic_tcu *tcu = to_ingenic_tcu(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	if (next > 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	regmap_write(tcu->map, TCU_REG_TDFRc(timer->channel), next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	regmap_write(tcu->map, TCU_REG_TCNTc(timer->channel), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	regmap_write(tcu->map, TCU_REG_TESR, BIT(timer->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void ingenic_per_cpu_event_handler(void *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct clock_event_device *cevt = (struct clock_event_device *) info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	cevt->event_handler(cevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static irqreturn_t ingenic_tcu_cevt_cb(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct ingenic_tcu_timer *timer = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct ingenic_tcu *tcu = to_ingenic_tcu(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	call_single_data_t *csd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	regmap_write(tcu->map, TCU_REG_TECR, BIT(timer->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (timer->cevt.event_handler) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		csd = &per_cpu(ingenic_cevt_csd, timer->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		csd->info = (void *) &timer->cevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		csd->func = ingenic_per_cpu_event_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		smp_call_function_single_async(timer->cpu, csd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct clk *ingenic_tcu_get_clock(struct device_node *np, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct of_phandle_args args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	args.np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	args.args_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	args.args[0] = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return of_clk_get_from_provider(&args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int ingenic_tcu_setup_cevt(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct ingenic_tcu *tcu = ingenic_tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct ingenic_tcu_timer *timer = &tcu->timers[cpu];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	unsigned int timer_virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	timer->clk = ingenic_tcu_get_clock(tcu->np, timer->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (IS_ERR(timer->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return PTR_ERR(timer->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	err = clk_prepare_enable(timer->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		goto err_clk_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	rate = clk_get_rate(timer->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (!rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	domain = irq_find_host(tcu->np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	timer_virq = irq_create_mapping(domain, timer->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (!timer_virq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	snprintf(timer->name, sizeof(timer->name), "TCU%u", timer->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	err = request_irq(timer_virq, ingenic_tcu_cevt_cb, IRQF_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			  timer->name, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		goto err_irq_dispose_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	timer->cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	timer->cevt.cpumask = cpumask_of(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	timer->cevt.features = CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	timer->cevt.name = timer->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	timer->cevt.rating = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	timer->cevt.set_state_shutdown = ingenic_tcu_cevt_set_state_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	timer->cevt.set_next_event = ingenic_tcu_cevt_set_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	clockevents_config_and_register(&timer->cevt, rate, 10, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) err_irq_dispose_mapping:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	irq_dispose_mapping(timer_virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	clk_disable_unprepare(timer->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) err_clk_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	clk_put(timer->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int __init ingenic_tcu_clocksource_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 					       struct ingenic_tcu *tcu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	unsigned int channel = tcu->cs_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct clocksource *cs = &tcu->cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	tcu->cs_clk = ingenic_tcu_get_clock(np, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (IS_ERR(tcu->cs_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		return PTR_ERR(tcu->cs_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	err = clk_prepare_enable(tcu->cs_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		goto err_clk_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	rate = clk_get_rate(tcu->cs_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (!rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	/* Reset channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	regmap_update_bits(tcu->map, TCU_REG_TCSRc(channel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			   0xffff & ~TCU_TCSR_RESERVED_BITS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/* Reset counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	regmap_write(tcu->map, TCU_REG_TDFRc(channel), 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	regmap_write(tcu->map, TCU_REG_TCNTc(channel), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/* Enable channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	regmap_write(tcu->map, TCU_REG_TESR, BIT(channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	cs->name = "ingenic-timer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	cs->rating = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	cs->mask = CLOCKSOURCE_MASK(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	cs->read = ingenic_tcu_timer_cs_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	err = clocksource_register_hz(cs, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	clk_disable_unprepare(tcu->cs_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) err_clk_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	clk_put(tcu->cs_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const struct ingenic_soc_info jz4740_soc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.num_channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct ingenic_soc_info jz4725b_soc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.num_channels = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const struct of_device_id ingenic_tcu_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	{ .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	{ .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	{ .compatible = "ingenic,jz4770-tcu", .data = &jz4740_soc_info, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	{ .compatible = "ingenic,x1000-tcu", .data = &jz4740_soc_info, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int __init ingenic_tcu_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	const struct of_device_id *id = of_match_node(ingenic_tcu_of_match, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	const struct ingenic_soc_info *soc_info = id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	struct ingenic_tcu_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	struct ingenic_tcu *tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	int ret, last_bit = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	of_node_clear_flag(np, OF_POPULATED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	map = device_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (IS_ERR(map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		return PTR_ERR(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	tcu = kzalloc(struct_size(tcu, timers, num_possible_cpus()),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		      GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (!tcu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	 * Enable all TCU channels for PWM use by default except channels 0/1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	 * and channel 2 if target CPU is JZ4780/X2000 and SMP is selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	tcu->pwm_channels_mask = GENMASK(soc_info->num_channels - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 					 num_possible_cpus() + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	of_property_read_u32(np, "ingenic,pwm-channels-mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			     (u32 *)&tcu->pwm_channels_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	/* Verify that we have at least num_possible_cpus() + 1 free channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	if (hweight8(tcu->pwm_channels_mask) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			soc_info->num_channels - num_possible_cpus() + 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		pr_crit("%s: Invalid PWM channel mask: 0x%02lx\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			tcu->pwm_channels_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		goto err_free_ingenic_tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	tcu->map = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	tcu->np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	ingenic_tcu = tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	for (cpu = 0; cpu < num_possible_cpus(); cpu++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		timer = &tcu->timers[cpu];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		timer->cpu = cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		timer->channel = find_next_zero_bit(&tcu->pwm_channels_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 						  soc_info->num_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 						  last_bit + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		last_bit = timer->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	tcu->cs_channel = find_next_zero_bit(&tcu->pwm_channels_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 					     soc_info->num_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 					     last_bit + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	ret = ingenic_tcu_clocksource_init(np, tcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		pr_crit("%s: Unable to init clocksource: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		goto err_free_ingenic_tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	/* Setup clock events on each CPU core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "Ingenic XBurst: online",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 				ingenic_tcu_setup_cevt, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		pr_crit("%s: Unable to start CPU timers: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		goto err_tcu_clocksource_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	/* Register the sched_clock at the end as there's no way to undo it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	rate = clk_get_rate(tcu->cs_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	sched_clock_register(ingenic_tcu_timer_read, 16, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) err_tcu_clocksource_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	clocksource_unregister(&tcu->cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	clk_disable_unprepare(tcu->cs_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	clk_put(tcu->cs_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) err_free_ingenic_tcu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	kfree(tcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) TIMER_OF_DECLARE(jz4740_tcu_intc,  "ingenic,jz4740-tcu",  ingenic_tcu_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) TIMER_OF_DECLARE(jz4725b_tcu_intc, "ingenic,jz4725b-tcu", ingenic_tcu_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) TIMER_OF_DECLARE(jz4770_tcu_intc,  "ingenic,jz4770-tcu",  ingenic_tcu_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) TIMER_OF_DECLARE(x1000_tcu_intc,  "ingenic,x1000-tcu",  ingenic_tcu_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int __init ingenic_tcu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	platform_set_drvdata(pdev, ingenic_tcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int __maybe_unused ingenic_tcu_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	struct ingenic_tcu *tcu = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	clk_disable(tcu->cs_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	for (cpu = 0; cpu < num_online_cpus(); cpu++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		clk_disable(tcu->timers[cpu].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int __maybe_unused ingenic_tcu_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	struct ingenic_tcu *tcu = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	for (cpu = 0; cpu < num_online_cpus(); cpu++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		ret = clk_enable(tcu->timers[cpu].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 			goto err_timer_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	ret = clk_enable(tcu->cs_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		goto err_timer_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) err_timer_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	for (; cpu > 0; cpu--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		clk_disable(tcu->timers[cpu - 1].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct dev_pm_ops __maybe_unused ingenic_tcu_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	/* _noirq: We want the TCU clocks to be gated last / ungated first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	.suspend_noirq = ingenic_tcu_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.resume_noirq  = ingenic_tcu_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static struct platform_driver ingenic_tcu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		.name	= "ingenic-tcu-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		.pm	= &ingenic_tcu_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		.of_match_table = ingenic_tcu_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) builtin_platform_driver_probe(ingenic_tcu_driver, ingenic_tcu_probe);