Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Ingenic XBurst SoCs SYSOST clocks driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <dt-bindings/clock/ingenic,sysost.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* OST register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define OST_REG_OSTCCR			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define OST_REG_OSTCR			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define OST_REG_OSTFR			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define OST_REG_OSTMR			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define OST_REG_OST1DFR			0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define OST_REG_OST1CNT			0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define OST_REG_OST2CNTL		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define OST_REG_OSTCNT2HBUF		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define OST_REG_OSTESR			0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define OST_REG_OSTECR			0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* bits within the OSTCCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define OSTCCR_PRESCALE1_MASK	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define OSTCCR_PRESCALE2_MASK	0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define OSTCCR_PRESCALE1_LSB	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define OSTCCR_PRESCALE2_LSB	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* bits within the OSTCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define OSTCR_OST1CLR			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define OSTCR_OST2CLR			BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* bits within the OSTFR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define OSTFR_FFLAG				BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* bits within the OSTMR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define OSTMR_FMASK				BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* bits within the OSTESR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define OSTESR_OST1ENS			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define OSTESR_OST2ENS			BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* bits within the OSTECR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define OSTECR_OST1ENC			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define OSTECR_OST2ENC			BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) struct ingenic_soc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) struct ingenic_ost_clk_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct clk_init_data init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u8 ostccr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) struct ingenic_ost_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct ingenic_ost *ost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	const struct ingenic_ost_clk_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) struct ingenic_ost {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	const struct ingenic_soc_info *soc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct clk *clk, *percpu_timer_clk, *global_timer_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct clock_event_device cevt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct clocksource cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	char name[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct clk_hw_onecell_data *clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static struct ingenic_ost *ingenic_ost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static inline struct ingenic_ost_clk *to_ost_clk(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return container_of(hw, struct ingenic_ost_clk, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static unsigned long ingenic_ost_percpu_timer_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct ingenic_ost_clk *ost_clk = to_ost_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	const struct ingenic_ost_clk_info *info = ost_clk->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	unsigned int prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	prescale = readl(ost_clk->ost->base + info->ostccr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	prescale = (prescale & OSTCCR_PRESCALE1_MASK) >> OSTCCR_PRESCALE1_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return parent_rate >> (prescale * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static unsigned long ingenic_ost_global_timer_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct ingenic_ost_clk *ost_clk = to_ost_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	const struct ingenic_ost_clk_info *info = ost_clk->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	unsigned int prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	prescale = readl(ost_clk->ost->base + info->ostccr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	prescale = (prescale & OSTCCR_PRESCALE2_MASK) >> OSTCCR_PRESCALE2_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	return parent_rate >> (prescale * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static u8 ingenic_ost_get_prescale(unsigned long rate, unsigned long req_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u8 prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	for (prescale = 0; prescale < 2; prescale++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		if ((rate >> (prescale * 2)) <= req_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			return prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	return 2; /* /16 divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static long ingenic_ost_round_rate(struct clk_hw *hw, unsigned long req_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	unsigned long rate = *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	u8 prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (req_rate > rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	prescale = ingenic_ost_get_prescale(rate, req_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return rate >> (prescale * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int ingenic_ost_percpu_timer_set_rate(struct clk_hw *hw, unsigned long req_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct ingenic_ost_clk *ost_clk = to_ost_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	const struct ingenic_ost_clk_info *info = ost_clk->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	u8 prescale = ingenic_ost_get_prescale(parent_rate, req_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	val = readl(ost_clk->ost->base + info->ostccr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	val = (val & ~OSTCCR_PRESCALE1_MASK) | (prescale << OSTCCR_PRESCALE1_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	writel(val, ost_clk->ost->base + info->ostccr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int ingenic_ost_global_timer_set_rate(struct clk_hw *hw, unsigned long req_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct ingenic_ost_clk *ost_clk = to_ost_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	const struct ingenic_ost_clk_info *info = ost_clk->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	u8 prescale = ingenic_ost_get_prescale(parent_rate, req_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	val = readl(ost_clk->ost->base + info->ostccr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	val = (val & ~OSTCCR_PRESCALE2_MASK) | (prescale << OSTCCR_PRESCALE2_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	writel(val, ost_clk->ost->base + info->ostccr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct clk_ops ingenic_ost_percpu_timer_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.recalc_rate	= ingenic_ost_percpu_timer_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.round_rate		= ingenic_ost_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.set_rate		= ingenic_ost_percpu_timer_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const struct clk_ops ingenic_ost_global_timer_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.recalc_rate	= ingenic_ost_global_timer_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.round_rate		= ingenic_ost_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.set_rate		= ingenic_ost_global_timer_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const char * const ingenic_ost_clk_parents[] = { "ext" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct ingenic_ost_clk_info ingenic_ost_clk_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	[OST_CLK_PERCPU_TIMER] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		.init_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			.name = "percpu timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			.parent_names = ingenic_ost_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			.num_parents = ARRAY_SIZE(ingenic_ost_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			.ops = &ingenic_ost_percpu_timer_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			.flags = CLK_SET_RATE_UNGATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.ostccr_reg = OST_REG_OSTCCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	[OST_CLK_GLOBAL_TIMER] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.init_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			.name = "global timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			.parent_names = ingenic_ost_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			.num_parents = ARRAY_SIZE(ingenic_ost_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			.ops = &ingenic_ost_global_timer_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			.flags = CLK_SET_RATE_UNGATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.ostccr_reg = OST_REG_OSTCCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static u64 notrace ingenic_ost_global_timer_read_cntl(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct ingenic_ost *ost = ingenic_ost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	count = readl(ost->base + OST_REG_OST2CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static u64 notrace ingenic_ost_clocksource_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	return ingenic_ost_global_timer_read_cntl();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static inline struct ingenic_ost *to_ingenic_ost(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return container_of(evt, struct ingenic_ost, cevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int ingenic_ost_cevt_set_state_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct ingenic_ost *ost = to_ingenic_ost(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	writel(OSTECR_OST1ENC, ost->base + OST_REG_OSTECR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int ingenic_ost_cevt_set_next(unsigned long next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 				     struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct ingenic_ost *ost = to_ingenic_ost(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	writel((u32)~OSTFR_FFLAG, ost->base + OST_REG_OSTFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	writel(next, ost->base + OST_REG_OST1DFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	writel(OSTCR_OST1CLR, ost->base + OST_REG_OSTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	writel(OSTESR_OST1ENS, ost->base + OST_REG_OSTESR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	writel((u32)~OSTMR_FMASK, ost->base + OST_REG_OSTMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static irqreturn_t ingenic_ost_cevt_cb(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	struct ingenic_ost *ost = to_ingenic_ost(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	writel(OSTECR_OST1ENC, ost->base + OST_REG_OSTECR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (evt->event_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int __init ingenic_ost_register_clock(struct ingenic_ost *ost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			unsigned int idx, const struct ingenic_ost_clk_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			struct clk_hw_onecell_data *clocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct ingenic_ost_clk *ost_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	int val, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	ost_clk = kzalloc(sizeof(*ost_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (!ost_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	ost_clk->hw.init = &info->init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	ost_clk->idx = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	ost_clk->info = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	ost_clk->ost = ost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	/* Reset clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	val = readl(ost->base + info->ostccr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	val &= ~(OSTCCR_PRESCALE1_MASK | OSTCCR_PRESCALE2_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	writel(val, ost->base + info->ostccr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	err = clk_hw_register(NULL, &ost_clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		kfree(ost_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	clocks->hws[idx] = &ost_clk->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static struct clk * __init ingenic_ost_get_clock(struct device_node *np, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	struct of_phandle_args args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	args.np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	args.args_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	args.args[0] = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	return of_clk_get_from_provider(&args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int __init ingenic_ost_percpu_timer_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 					 struct ingenic_ost *ost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	unsigned int timer_virq, channel = OST_CLK_PERCPU_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	ost->percpu_timer_clk = ingenic_ost_get_clock(np, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (IS_ERR(ost->percpu_timer_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		return PTR_ERR(ost->percpu_timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	err = clk_prepare_enable(ost->percpu_timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		goto err_clk_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	rate = clk_get_rate(ost->percpu_timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (!rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	timer_virq = of_irq_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (!timer_virq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	snprintf(ost->name, sizeof(ost->name), "OST percpu timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	err = request_irq(timer_virq, ingenic_ost_cevt_cb, IRQF_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			  ost->name, &ost->cevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		goto err_irq_dispose_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	ost->cevt.cpumask = cpumask_of(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	ost->cevt.features = CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	ost->cevt.name = ost->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	ost->cevt.rating = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	ost->cevt.set_state_shutdown = ingenic_ost_cevt_set_state_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	ost->cevt.set_next_event = ingenic_ost_cevt_set_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	clockevents_config_and_register(&ost->cevt, rate, 4, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) err_irq_dispose_mapping:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	irq_dispose_mapping(timer_virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	clk_disable_unprepare(ost->percpu_timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) err_clk_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	clk_put(ost->percpu_timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static int __init ingenic_ost_global_timer_init(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 					       struct ingenic_ost *ost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	unsigned int channel = OST_CLK_GLOBAL_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	struct clocksource *cs = &ost->cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	ost->global_timer_clk = ingenic_ost_get_clock(np, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	if (IS_ERR(ost->global_timer_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		return PTR_ERR(ost->global_timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	err = clk_prepare_enable(ost->global_timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		goto err_clk_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	rate = clk_get_rate(ost->global_timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	if (!rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	/* Clear counter CNT registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	writel(OSTCR_OST2CLR, ost->base + OST_REG_OSTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	/* Enable OST channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	writel(OSTESR_OST2ENS, ost->base + OST_REG_OSTESR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	cs->name = "ingenic-ost";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	cs->rating = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	cs->mask = CLOCKSOURCE_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	cs->read = ingenic_ost_clocksource_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	err = clocksource_register_hz(cs, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	clk_disable_unprepare(ost->global_timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) err_clk_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	clk_put(ost->global_timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static const struct ingenic_soc_info x1000_soc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	.num_channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static const struct of_device_id __maybe_unused ingenic_ost_of_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	{ .compatible = "ingenic,x1000-ost", .data = &x1000_soc_info, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int __init ingenic_ost_probe(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	const struct of_device_id *id = of_match_node(ingenic_ost_of_match, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	struct ingenic_ost *ost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	ost = kzalloc(sizeof(*ost), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	if (!ost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	ost->base = of_io_request_and_map(np, 0, of_node_full_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	if (IS_ERR(ost->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		pr_err("%s: Failed to map OST registers\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		ret = PTR_ERR(ost->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		goto err_free_ost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	ost->clk = of_clk_get_by_name(np, "ost");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	if (IS_ERR(ost->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		ret = PTR_ERR(ost->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		pr_crit("%s: Cannot get OST clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		goto err_free_ost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	ret = clk_prepare_enable(ost->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		pr_crit("%s: Unable to enable OST clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		goto err_put_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	ost->soc_info = id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	ost->clocks = kzalloc(struct_size(ost->clocks, hws, ost->soc_info->num_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 			      GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	if (!ost->clocks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	ost->clocks->num = ost->soc_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	for (i = 0; i < ost->clocks->num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		ret = ingenic_ost_register_clock(ost, i, &ingenic_ost_clk_info[i], ost->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 			pr_crit("%s: Cannot register clock %d\n", __func__, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 			goto err_unregister_ost_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, ost->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		pr_crit("%s: Cannot add OF clock provider\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		goto err_unregister_ost_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	ingenic_ost = ost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) err_unregister_ost_clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	for (i = 0; i < ost->clocks->num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		if (ost->clocks->hws[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 			clk_hw_unregister(ost->clocks->hws[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	kfree(ost->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	clk_disable_unprepare(ost->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) err_put_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	clk_put(ost->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) err_free_ost:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	kfree(ost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static int __init ingenic_ost_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	struct ingenic_ost *ost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	ret = ingenic_ost_probe(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		pr_crit("%s: Failed to initialize OST clocks: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	of_node_clear_flag(np, OF_POPULATED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	ost = ingenic_ost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	if (IS_ERR(ost))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		return PTR_ERR(ost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	ret = ingenic_ost_global_timer_init(np, ost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 		pr_crit("%s: Unable to init global timer: %x\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		goto err_free_ingenic_ost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	ret = ingenic_ost_percpu_timer_init(np, ost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		goto err_ost_global_timer_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	/* Register the sched_clock at the end as there's no way to undo it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	rate = clk_get_rate(ost->global_timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	sched_clock_register(ingenic_ost_global_timer_read_cntl, 32, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) err_ost_global_timer_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	clocksource_unregister(&ost->cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	clk_disable_unprepare(ost->global_timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	clk_put(ost->global_timer_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) err_free_ingenic_ost:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	kfree(ost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) TIMER_OF_DECLARE(x1000_ost,  "ingenic,x1000-ost",  ingenic_ost_init);