^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i8253 PIT clocksource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/timex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i8253.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Protects access to I/O ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 0040-0043 : timer0, i8253 / i8254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 0061-0061 : NMI Control Register which contains two speaker control bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) DEFINE_RAW_SPINLOCK(i8253_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) EXPORT_SYMBOL(i8253_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Handle PIT quirk in pit_shutdown() where zeroing the counter register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * restarts the PIT, negating the shutdown. On platforms with the quirk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * platform specific code can set this to false.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) bool i8253_clear_counter_on_shutdown __ro_after_init = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifdef CONFIG_CLKSRC_I8253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Since the PIT overflows every tick, its not very useful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * to just read by itself. So use jiffies to emulate a free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * running counter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static u64 i8253_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int old_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static u32 old_jifs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 jifs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) raw_spin_lock_irqsave(&i8253_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Although our caller may have the read side of jiffies_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * this is now a seqlock, and we are cheating in this routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * by having side effects on state that we cannot undo if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * there is a collision on the seqlock and our caller has to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * retry. (Namely, old_jifs and old_count.) So we must treat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * jiffies as volatile despite the lock. We read jiffies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * before latching the timer count to guarantee that although
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * the jiffies value might be older than the count (that is,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * the counter may underflow between the last point where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * jiffies was incremented and the point where we latch the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * count), it cannot be newer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) jifs = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) outb_p(0x00, PIT_MODE); /* latch the count ASAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) count = inb_p(PIT_CH0); /* read the latched count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) count |= inb_p(PIT_CH0) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* VIA686a test code... reset the latch if count > max + 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (count > PIT_LATCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) outb_p(0x34, PIT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) outb_p(PIT_LATCH & 0xff, PIT_CH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) outb_p(PIT_LATCH >> 8, PIT_CH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) count = PIT_LATCH - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * It's possible for count to appear to go the wrong way for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * couple of reasons:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * 1. The timer counter underflows, but we haven't handled the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * resulting interrupt and incremented jiffies yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * 2. Hardware problem with the timer, not giving us continuous time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * the counter does small "jumps" upwards on some Pentium systems,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * (see c't 95/10 page 335 for Neptun bug.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Previous attempts to handle these cases intelligently were
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * buggy, so we just do the simple thing now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (count > old_count && jifs == old_jifs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) count = old_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) old_count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) old_jifs = jifs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) raw_spin_unlock_irqrestore(&i8253_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) count = (PIT_LATCH - 1) - count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return (u64)(jifs * PIT_LATCH) + count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static struct clocksource i8253_cs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .name = "pit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .rating = 110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .read = i8253_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .mask = CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int __init clocksource_i8253_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return clocksource_register_hz(&i8253_cs, PIT_TICK_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #ifdef CONFIG_CLKEVT_I8253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int pit_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (!clockevent_state_oneshot(evt) && !clockevent_state_periodic(evt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) raw_spin_lock(&i8253_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) outb_p(0x30, PIT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (i8253_clear_counter_on_shutdown) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) outb_p(0, PIT_CH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) outb_p(0, PIT_CH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) raw_spin_unlock(&i8253_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int pit_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) raw_spin_lock(&i8253_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) outb_p(0x38, PIT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) raw_spin_unlock(&i8253_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int pit_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) raw_spin_lock(&i8253_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* binary, mode 2, LSB/MSB, ch 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) outb_p(0x34, PIT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) outb_p(PIT_LATCH & 0xff, PIT_CH0); /* LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) outb_p(PIT_LATCH >> 8, PIT_CH0); /* MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) raw_spin_unlock(&i8253_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * Program the next event in oneshot mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Delta is given in PIT ticks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) raw_spin_lock(&i8253_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) outb_p(delta & 0xff , PIT_CH0); /* LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) outb_p(delta >> 8 , PIT_CH0); /* MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) raw_spin_unlock(&i8253_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * On UP the PIT can serve all of the possible timer functions. On SMP systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * it can be solely used for the global tick.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct clock_event_device i8253_clockevent = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .name = "pit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .features = CLOCK_EVT_FEAT_PERIODIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .set_state_shutdown = pit_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .set_state_periodic = pit_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .set_next_event = pit_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Initialize the conversion factor and the min/max deltas of the clock event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * structure and register the clock event source with the framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void __init clockevent_i8253_init(bool oneshot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (oneshot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) i8253_clockevent.features |= CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) i8253_clockevent.set_state_oneshot = pit_set_oneshot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Start pit with the boot cpu mask. x86 might make it global
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * when it is used as broadcast device later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) i8253_clockevent.cpumask = cpumask_of(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) clockevents_config_and_register(&i8253_clockevent, PIT_TICK_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 0xF, 0x7FFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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