^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * H8S TPU Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2015 Yoshinori Sato <ysato@users.sourcefoge.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TCR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TSR 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TCNT 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TCFV 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct tpu_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct clocksource cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void __iomem *mapbase1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) void __iomem *mapbase2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int cs_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static inline unsigned long read_tcnt32(struct tpu_priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned long tcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) tcnt = ioread16be(p->mapbase1 + TCNT) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) tcnt |= ioread16be(p->mapbase2 + TCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return tcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int tpu_get_counter(struct tpu_priv *p, unsigned long long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long v1, v2, v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int o1, o2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) o1 = ioread8(p->mapbase1 + TSR) & TCFV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Make sure the timer value is stable. Stolen from acpi_pm.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) o2 = o1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) v1 = read_tcnt32(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) v2 = read_tcnt32(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) v3 = read_tcnt32(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) o1 = ioread8(p->mapbase1 + TSR) & TCFV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *val = v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return o1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline struct tpu_priv *cs_to_priv(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return container_of(cs, struct tpu_priv, cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static u64 tpu_clocksource_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct tpu_priv *p = cs_to_priv(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) raw_spin_lock_irqsave(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (tpu_get_counter(p, &value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) value += 0x100000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) raw_spin_unlock_irqrestore(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int tpu_clocksource_enable(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct tpu_priv *p = cs_to_priv(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) WARN_ON(p->cs_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) iowrite16be(0, p->mapbase1 + TCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) iowrite16be(0, p->mapbase2 + TCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) iowrite8(0x0f, p->mapbase1 + TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) iowrite8(0x03, p->mapbase2 + TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) p->cs_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static void tpu_clocksource_disable(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct tpu_priv *p = cs_to_priv(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) WARN_ON(!p->cs_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) iowrite8(0, p->mapbase1 + TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) iowrite8(0, p->mapbase2 + TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) p->cs_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct tpu_priv tpu_priv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .cs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .name = "H8S_TPU",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .rating = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .read = tpu_clocksource_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .enable = tpu_clocksource_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .disable = tpu_clocksource_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CH_L 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CH_H 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int __init h8300_tpu_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void __iomem *base[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) clk = of_clk_get(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pr_err("failed to get clock for clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) base[CH_L] = of_iomap(node, CH_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (!base[CH_L]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pr_err("failed to map registers for clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) goto free_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) base[CH_H] = of_iomap(node, CH_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (!base[CH_H]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) pr_err("failed to map registers for clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) goto unmap_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) tpu_priv.mapbase1 = base[CH_L];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) tpu_priv.mapbase2 = base[CH_H];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return clocksource_register_hz(&tpu_priv.cs, clk_get_rate(clk) / 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unmap_L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) iounmap(base[CH_H]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) free_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) TIMER_OF_DECLARE(h8300_tpu, "renesas,tpu", h8300_tpu_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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