^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/h8300/kernel/cpu/timer/timer8.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Yoshinori Sato <ysato@users.sourcefoge.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 8bit Timer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define _8TCR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define _8TCSR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TCORA 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TCORB 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define _8TCNT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CMIEA 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CMFA 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FLAG_STARTED (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SCALE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define bset(b, a) iowrite8(ioread8(a) | (1 << (b)), (a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define bclr(b, a) iowrite8(ioread8(a) & ~(1 << (b)), (a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct timer8_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct clock_event_device ced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void __iomem *mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static irqreturn_t timer8_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct timer8_priv *p = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (clockevent_state_oneshot(&p->ced))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) iowrite16be(0x0000, p->mapbase + _8TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) p->ced.event_handler(&p->ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) bclr(CMFA, p->mapbase + _8TCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (delta >= 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pr_warn("delta out of range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) bclr(CMIEA, p->mapbase + _8TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) iowrite16be(delta, p->mapbase + TCORA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) iowrite16be(0x0000, p->mapbase + _8TCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) bclr(CMFA, p->mapbase + _8TCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) bset(CMIEA, p->mapbase + _8TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int timer8_enable(struct timer8_priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) iowrite16be(0xffff, p->mapbase + TCORA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) iowrite16be(0x0000, p->mapbase + _8TCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) iowrite16be(0x0c02, p->mapbase + _8TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int timer8_start(struct timer8_priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if ((p->flags & FLAG_STARTED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ret = timer8_enable(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) p->flags |= FLAG_STARTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void timer8_stop(struct timer8_priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) iowrite16be(0x0000, p->mapbase + _8TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline struct timer8_priv *ced_to_priv(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return container_of(ced, struct timer8_priv, ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) timer8_start(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) timer8_set_next(p, delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int timer8_clock_event_shutdown(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) timer8_stop(ced_to_priv(ced));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int timer8_clock_event_periodic(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct timer8_priv *p = ced_to_priv(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) pr_info("%s: used for periodic clock events\n", ced->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) timer8_stop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) timer8_clock_event_start(p, (p->rate + HZ/2) / HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int timer8_clock_event_oneshot(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct timer8_priv *p = ced_to_priv(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pr_info("%s: used for oneshot clock events\n", ced->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) timer8_stop(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) timer8_clock_event_start(p, 0x10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int timer8_clock_event_next(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct timer8_priv *p = ced_to_priv(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) BUG_ON(!clockevent_state_oneshot(ced));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) timer8_set_next(p, delta - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct timer8_priv timer8_priv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .ced = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .name = "h8300_8timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .rating = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .set_next_event = timer8_clock_event_next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .set_state_shutdown = timer8_clock_event_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .set_state_periodic = timer8_clock_event_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .set_state_oneshot = timer8_clock_event_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int __init h8300_8timer_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) clk = of_clk_get(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pr_err("failed to get clock for clockevent\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pr_err("failed to map registers for clockevent\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) goto free_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pr_err("failed to get irq for clockevent\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) goto unmap_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) timer8_priv.mapbase = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) timer8_priv.rate = clk_get_rate(clk) / SCALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (!timer8_priv.rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pr_err("Failed to get rate for the clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) goto unmap_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (request_irq(irq, timer8_interrupt, IRQF_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) timer8_priv.ced.name, &timer8_priv) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pr_err("failed to request irq %d for clockevent\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) goto unmap_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) clockevents_config_and_register(&timer8_priv.ced,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) timer8_priv.rate, 1, 0x0000ffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unmap_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) free_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) TIMER_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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