^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * H8/300 16bit Timer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2015 Yoshinori Sato <ysato@users.sourcefoge.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TSTR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TISRC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TCR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TCNT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define bset(b, a) iowrite8(ioread8(a) | (1 << (b)), (a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define bclr(b, a) iowrite8(ioread8(a) & ~(1 << (b)), (a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct timer16_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct clocksource cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned long total_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void __iomem *mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *mapcommon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned short cs_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned char enb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned char ovf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned char ovie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static unsigned long timer16_get_counter(struct timer16_priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned short v1, v2, v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned char o1, o2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) o1 = ioread8(p->mapcommon + TISRC) & p->ovf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Make sure the timer value is stable. Stolen from acpi_pm.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) o2 = o1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) v1 = ioread16be(p->mapbase + TCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) v2 = ioread16be(p->mapbase + TCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) v3 = ioread16be(p->mapbase + TCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) o1 = ioread8(p->mapcommon + TISRC) & p->ovf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (likely(!o1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return v2 + 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static irqreturn_t timer16_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct timer16_priv *p = (struct timer16_priv *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) bclr(p->ovf, p->mapcommon + TISRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) p->total_cycles += 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static inline struct timer16_priv *cs_to_priv(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return container_of(cs, struct timer16_priv, cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static u64 timer16_clocksource_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct timer16_priv *p = cs_to_priv(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long raw, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) value = p->total_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) raw = timer16_get_counter(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return value + raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int timer16_enable(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct timer16_priv *p = cs_to_priv(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) WARN_ON(p->cs_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) p->total_cycles = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) iowrite16be(0x0000, p->mapbase + TCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) iowrite8(0x83, p->mapbase + TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) bset(p->ovie, p->mapcommon + TISRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) bset(p->enb, p->mapcommon + TSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) p->cs_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void timer16_disable(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct timer16_priv *p = cs_to_priv(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) WARN_ON(!p->cs_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bclr(p->ovie, p->mapcommon + TISRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bclr(p->enb, p->mapcommon + TSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) p->cs_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct timer16_priv timer16_priv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .cs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .name = "h8300_16timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .rating = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .read = timer16_clocksource_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .enable = timer16_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .disable = timer16_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define REG_CH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define REG_COMM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int __init h8300_16timer_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) void __iomem *base[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) clk = of_clk_get(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pr_err("failed to get clock for clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) base[REG_CH] = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (!base[REG_CH]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pr_err("failed to map registers for clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) goto free_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) base[REG_COMM] = of_iomap(node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (!base[REG_COMM]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pr_err("failed to map registers for clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) goto unmap_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pr_err("failed to get irq for clockevent\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) goto unmap_comm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) of_property_read_u32(node, "renesas,channel", &ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) timer16_priv.mapbase = base[REG_CH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) timer16_priv.mapcommon = base[REG_COMM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) timer16_priv.enb = ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) timer16_priv.ovf = ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) timer16_priv.ovie = 4 + ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = request_irq(irq, timer16_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) IRQF_TIMER, timer16_priv.cs.name, &timer16_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) pr_err("failed to request irq %d of clocksource\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) goto unmap_comm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) clocksource_register_hz(&timer16_priv.cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) clk_get_rate(clk) / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unmap_comm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) iounmap(base[REG_COMM]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unmap_ch:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) iounmap(base[REG_CH]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) free_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) TIMER_OF_DECLARE(h8300_16bit, "renesas,16bit-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) h8300_16timer_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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