Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Emma Mobile Timer Support - STI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2012 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) enum { USER_CLOCKSOURCE, USER_CLOCKEVENT, USER_NR };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct em_sti_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	unsigned int active[USER_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct clock_event_device ced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct clocksource cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define STI_CONTROL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define STI_COMPA_H 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define STI_COMPA_L 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define STI_COMPB_H 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define STI_COMPB_L 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define STI_COUNT_H 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define STI_COUNT_L 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define STI_COUNT_RAW_H 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define STI_COUNT_RAW_L 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define STI_SET_H 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define STI_SET_L 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define STI_INTSTATUS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define STI_INTRAWSTATUS 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define STI_INTENSET 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define STI_INTENCLR 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define STI_INTFFCLR 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static inline unsigned long em_sti_read(struct em_sti_priv *p, int offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	return ioread32(p->base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static inline void em_sti_write(struct em_sti_priv *p, int offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 				unsigned long value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	iowrite32(value, p->base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static int em_sti_enable(struct em_sti_priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/* enable clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	ret = clk_enable(p->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		dev_err(&p->pdev->dev, "cannot enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	/* reset the counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	em_sti_write(p, STI_SET_H, 0x40000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	em_sti_write(p, STI_SET_L, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/* mask and clear pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	em_sti_write(p, STI_INTENCLR, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	em_sti_write(p, STI_INTFFCLR, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/* enable updates of counter registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	em_sti_write(p, STI_CONTROL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static void em_sti_disable(struct em_sti_priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	/* mask interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	em_sti_write(p, STI_INTENCLR, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	/* stop clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	clk_disable(p->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static u64 em_sti_count(struct em_sti_priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u64 ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/* the STI hardware buffers the 48-bit count, but to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 * break it out into two 32-bit access the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 * must be accessed in a certain order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 * Always read STI_COUNT_H before STI_COUNT_L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	raw_spin_lock_irqsave(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ticks = (u64)(em_sti_read(p, STI_COUNT_H) & 0xffff) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	ticks |= em_sti_read(p, STI_COUNT_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	raw_spin_unlock_irqrestore(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	return ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static u64 em_sti_set_next(struct em_sti_priv *p, u64 next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	raw_spin_lock_irqsave(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	/* mask compare A interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	em_sti_write(p, STI_INTENCLR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* update compare A value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	em_sti_write(p, STI_COMPA_H, next >> 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	em_sti_write(p, STI_COMPA_L, next & 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	/* clear compare A interrupt source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	em_sti_write(p, STI_INTFFCLR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	/* unmask compare A interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	em_sti_write(p, STI_INTENSET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	raw_spin_unlock_irqrestore(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	return next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static irqreturn_t em_sti_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct em_sti_priv *p = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	p->ced.event_handler(&p->ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int em_sti_start(struct em_sti_priv *p, unsigned int user)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	int used_before;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	raw_spin_lock_irqsave(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	used_before = p->active[USER_CLOCKSOURCE] | p->active[USER_CLOCKEVENT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (!used_before)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		ret = em_sti_enable(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		p->active[user] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	raw_spin_unlock_irqrestore(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void em_sti_stop(struct em_sti_priv *p, unsigned int user)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	int used_before, used_after;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	raw_spin_lock_irqsave(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	used_before = p->active[USER_CLOCKSOURCE] | p->active[USER_CLOCKEVENT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	p->active[user] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	used_after = p->active[USER_CLOCKSOURCE] | p->active[USER_CLOCKEVENT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (used_before && !used_after)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		em_sti_disable(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	raw_spin_unlock_irqrestore(&p->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct em_sti_priv *cs_to_em_sti(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return container_of(cs, struct em_sti_priv, cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static u64 em_sti_clocksource_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	return em_sti_count(cs_to_em_sti(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int em_sti_clocksource_enable(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct em_sti_priv *p = cs_to_em_sti(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	return em_sti_start(p, USER_CLOCKSOURCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void em_sti_clocksource_disable(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	em_sti_stop(cs_to_em_sti(cs), USER_CLOCKSOURCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void em_sti_clocksource_resume(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	em_sti_clocksource_enable(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int em_sti_register_clocksource(struct em_sti_priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct clocksource *cs = &p->cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	cs->name = dev_name(&p->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	cs->rating = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	cs->read = em_sti_clocksource_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	cs->enable = em_sti_clocksource_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	cs->disable = em_sti_clocksource_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	cs->suspend = em_sti_clocksource_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	cs->resume = em_sti_clocksource_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	cs->mask = CLOCKSOURCE_MASK(48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	dev_info(&p->pdev->dev, "used as clock source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	clocksource_register_hz(cs, p->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct em_sti_priv *ced_to_em_sti(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return container_of(ced, struct em_sti_priv, ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int em_sti_clock_event_shutdown(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct em_sti_priv *p = ced_to_em_sti(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	em_sti_stop(p, USER_CLOCKEVENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int em_sti_clock_event_set_oneshot(struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct em_sti_priv *p = ced_to_em_sti(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	dev_info(&p->pdev->dev, "used for oneshot clock events\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	em_sti_start(p, USER_CLOCKEVENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int em_sti_clock_event_next(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 				   struct clock_event_device *ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	struct em_sti_priv *p = ced_to_em_sti(ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	u64 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	int safe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	next = em_sti_set_next(p, em_sti_count(p) + delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	safe = em_sti_count(p) < (next - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	return !safe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static void em_sti_register_clockevent(struct em_sti_priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct clock_event_device *ced = &p->ced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	ced->name = dev_name(&p->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	ced->features = CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	ced->rating = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	ced->cpumask = cpu_possible_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	ced->set_next_event = em_sti_clock_event_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	ced->set_state_shutdown = em_sti_clock_event_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	ced->set_state_oneshot = em_sti_clock_event_set_oneshot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	dev_info(&p->pdev->dev, "used for clock events\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	clockevents_config_and_register(ced, p->rate, 2, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int em_sti_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	struct em_sti_priv *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (p == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	p->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	platform_set_drvdata(pdev, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	/* map memory, let base point to the STI instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	p->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	if (IS_ERR(p->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		return PTR_ERR(p->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	ret = devm_request_irq(&pdev->dev, irq, em_sti_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			       IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			       dev_name(&pdev->dev), p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		dev_err(&pdev->dev, "failed to request low IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	/* get hold of clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	p->clk = devm_clk_get(&pdev->dev, "sclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (IS_ERR(p->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		dev_err(&pdev->dev, "cannot get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		return PTR_ERR(p->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	ret = clk_prepare(p->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		dev_err(&pdev->dev, "cannot prepare clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	ret = clk_enable(p->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		dev_err(&p->pdev->dev, "cannot enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		clk_unprepare(p->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	p->rate = clk_get_rate(p->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	clk_disable(p->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	raw_spin_lock_init(&p->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	em_sti_register_clockevent(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	em_sti_register_clocksource(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int em_sti_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	return -EBUSY; /* cannot unregister clockevent and clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const struct of_device_id em_sti_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	{ .compatible = "renesas,em-sti", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MODULE_DEVICE_TABLE(of, em_sti_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static struct platform_driver em_sti_device_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	.probe		= em_sti_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	.remove		= em_sti_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.name	= "em_sti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		.of_match_table = em_sti_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int __init em_sti_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	return platform_driver_register(&em_sti_device_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static void __exit em_sti_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	platform_driver_unregister(&em_sti_device_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) subsys_initcall(em_sti_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) module_exit(em_sti_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MODULE_AUTHOR("Magnus Damm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MODULE_DESCRIPTION("Renesas Emma Mobile STI Timer Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MODULE_LICENSE("GPL v2");