Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * (C) Copyright 2009 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Jacob Pan (jacob.jun.pan@intel.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Shared with ARM platforms, Jamie Iles, Picochip 2011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Support for the Synopsys DesignWare APB Timers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/dw_apb_timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define APBT_MIN_PERIOD			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define APBT_MIN_DELTA_USEC		200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define APBTMR_N_LOAD_COUNT		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define APBTMR_N_CURRENT_VALUE		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define APBTMR_N_CONTROL		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define APBTMR_N_EOI			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define APBTMR_N_INT_STATUS		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define APBTMRS_INT_STATUS		0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define APBTMRS_EOI			0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define APBTMRS_RAW_INT_STATUS		0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define APBTMRS_COMP_VERSION		0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define APBTMR_CONTROL_ENABLE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* 1: periodic, 0:free running. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define APBTMR_CONTROL_MODE_PERIODIC	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define APBTMR_CONTROL_INT		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static inline struct dw_apb_clock_event_device *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) ced_to_dw_apb_ced(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	return container_of(evt, struct dw_apb_clock_event_device, ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static inline struct dw_apb_clocksource *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) clocksource_to_dw_apb_clocksource(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	return container_of(cs, struct dw_apb_clocksource, cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static inline u32 apbt_readl(struct dw_apb_timer *timer, unsigned long offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	return readl(timer->base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static inline void apbt_writel(struct dw_apb_timer *timer, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			unsigned long offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	writel(val, timer->base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static inline u32 apbt_readl_relaxed(struct dw_apb_timer *timer, unsigned long offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	return readl_relaxed(timer->base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static inline void apbt_writel_relaxed(struct dw_apb_timer *timer, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			unsigned long offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	writel_relaxed(val, timer->base + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static void apbt_disable_int(struct dw_apb_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u32 ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	ctrl |= APBTMR_CONTROL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * dw_apb_clockevent_pause() - stop the clock_event_device from running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * @dw_ced:	The APB clock to stop generating events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) void dw_apb_clockevent_pause(struct dw_apb_clock_event_device *dw_ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	disable_irq(dw_ced->timer.irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	apbt_disable_int(&dw_ced->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static void apbt_eoi(struct dw_apb_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	apbt_readl_relaxed(timer, APBTMR_N_EOI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static irqreturn_t dw_apb_clockevent_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct clock_event_device *evt = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (!evt->event_handler) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		pr_info("Spurious APBT timer interrupt %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (dw_ced->eoi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		dw_ced->eoi(&dw_ced->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void apbt_enable_int(struct dw_apb_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	u32 ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/* clear pending intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	apbt_readl(timer, APBTMR_N_EOI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	ctrl &= ~APBTMR_CONTROL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int apbt_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	pr_debug("%s CPU %d state=shutdown\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		 cpumask_first(evt->cpumask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	ctrl &= ~APBTMR_CONTROL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int apbt_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	pr_debug("%s CPU %d state=oneshot\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		 cpumask_first(evt->cpumask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	 * set free running mode, this mode will let timer reload max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	 * timeout which will give time (3min on 25MHz clock) to rearm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	 * the next event, therefore emulate the one-shot mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	ctrl &= ~APBTMR_CONTROL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/* write again to set free running mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	 * DW APB p. 46, load counter with all 1s before starting free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	 * running mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	ctrl &= ~APBTMR_CONTROL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	ctrl |= APBTMR_CONTROL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int apbt_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	unsigned long period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	pr_debug("%s CPU %d state=periodic\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		 cpumask_first(evt->cpumask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 * DW APB p. 46, have to disable timer before load counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 * may cause sync problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ctrl &= ~APBTMR_CONTROL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	pr_debug("Setting clock period %lu for HZ %d\n", period, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	ctrl |= APBTMR_CONTROL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int apbt_resume(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	pr_debug("%s CPU %d state=resume\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		 cpumask_first(evt->cpumask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	apbt_enable_int(&dw_ced->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int apbt_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			   struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/* Disable timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	ctrl = apbt_readl_relaxed(&dw_ced->timer, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	ctrl &= ~APBTMR_CONTROL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	apbt_writel_relaxed(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	/* write new count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	apbt_writel_relaxed(&dw_ced->timer, delta, APBTMR_N_LOAD_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	ctrl |= APBTMR_CONTROL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	apbt_writel_relaxed(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  * dw_apb_clockevent_init() - use an APB timer as a clock_event_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  * @cpu:	The CPU the events will be targeted at or -1 if CPU affiliation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  *		isn't required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  * @name:	The name used for the timer and the IRQ for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  * @rating:	The rating to give the timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  * @base:	I/O base for the timer registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  * @irq:	The interrupt number to use for the timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)  * @freq:	The frequency that the timer counts at.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  * This creates a clock_event_device for using with the generic clock layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  * but does not start and register it.  This should be done with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  * dw_apb_clockevent_register() as the next step.  If this is the first time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  * it has been called for a timer then the IRQ will be requested, if not it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  * just be enabled to allow CPU hotplug to avoid repeatedly requesting and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  * releasing the IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct dw_apb_clock_event_device *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		       void __iomem *base, int irq, unsigned long freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct dw_apb_clock_event_device *dw_ced =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		kzalloc(sizeof(*dw_ced), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (!dw_ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	dw_ced->timer.base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	dw_ced->timer.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	dw_ced->timer.freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	clockevents_calc_mult_shift(&dw_ced->ced, freq, APBT_MIN_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	dw_ced->ced.max_delta_ns = clockevent_delta2ns(0x7fffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 						       &dw_ced->ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	dw_ced->ced.max_delta_ticks = 0x7fffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	dw_ced->ced.min_delta_ns = clockevent_delta2ns(5000, &dw_ced->ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	dw_ced->ced.min_delta_ticks = 5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	dw_ced->ced.cpumask = cpu < 0 ? cpu_possible_mask : cpumask_of(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	dw_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	dw_ced->ced.set_state_shutdown = apbt_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	dw_ced->ced.set_state_periodic = apbt_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	dw_ced->ced.set_state_oneshot = apbt_set_oneshot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	dw_ced->ced.set_state_oneshot_stopped = apbt_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	dw_ced->ced.tick_resume = apbt_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	dw_ced->ced.set_next_event = apbt_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	dw_ced->ced.irq = dw_ced->timer.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	dw_ced->ced.rating = rating;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	dw_ced->ced.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	dw_ced->eoi = apbt_eoi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	err = request_irq(irq, dw_apb_clockevent_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			  IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			  dw_ced->ced.name, &dw_ced->ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		pr_err("failed to request timer irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		kfree(dw_ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		dw_ced = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	return dw_ced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  * dw_apb_clockevent_resume() - resume a clock that has been paused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)  * @dw_ced:	The APB clock to resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	enable_irq(dw_ced->timer.irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)  * dw_apb_clockevent_stop() - stop the clock_event_device and release the IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)  * @dw_ced:	The APB clock to stop generating the events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	free_irq(dw_ced->timer.irq, &dw_ced->ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)  * dw_apb_clockevent_register() - register the clock with the generic layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)  * @dw_ced:	The APB clock to register as a clock_event_device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) void dw_apb_clockevent_register(struct dw_apb_clock_event_device *dw_ced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	apbt_writel(&dw_ced->timer, 0, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	clockevents_register_device(&dw_ced->ced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	apbt_enable_int(&dw_ced->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)  * dw_apb_clocksource_start() - start the clocksource counting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)  * @dw_cs:	The clocksource to start.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)  * This is used to start the clocksource before registration and can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)  * to enable calibration of timers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	 * start count down from 0xffff_ffff. this is done by toggling the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	 * enable bit then load initial load count to ~0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	u32 ctrl = apbt_readl(&dw_cs->timer, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	ctrl &= ~APBTMR_CONTROL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	apbt_writel(&dw_cs->timer, ~0, APBTMR_N_LOAD_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	/* enable, mask interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	/* read it once to get cached counter value initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	dw_apb_clocksource_read(dw_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static u64 __apbt_read_clocksource(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	u32 current_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	struct dw_apb_clocksource *dw_cs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		clocksource_to_dw_apb_clocksource(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	current_count = apbt_readl_relaxed(&dw_cs->timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 					APBTMR_N_CURRENT_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	return (u64)~current_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void apbt_restart_clocksource(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	struct dw_apb_clocksource *dw_cs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		clocksource_to_dw_apb_clocksource(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	dw_apb_clocksource_start(dw_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)  * dw_apb_clocksource_init() - use an APB timer as a clocksource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)  * @rating:	The rating to give the clocksource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)  * @name:	The name for the clocksource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)  * @base:	The I/O base for the timer registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)  * @freq:	The frequency that the timer counts at.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)  * This creates a clocksource using an APB timer but does not yet register it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)  * with the clocksource system.  This should be done with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)  * dw_apb_clocksource_register() as the next step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct dw_apb_clocksource *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dw_apb_clocksource_init(unsigned rating, const char *name, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 			unsigned long freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	struct dw_apb_clocksource *dw_cs = kzalloc(sizeof(*dw_cs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if (!dw_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	dw_cs->timer.base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	dw_cs->timer.freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	dw_cs->cs.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	dw_cs->cs.rating = rating;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	dw_cs->cs.read = __apbt_read_clocksource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	dw_cs->cs.mask = CLOCKSOURCE_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	dw_cs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	dw_cs->cs.resume = apbt_restart_clocksource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	return dw_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)  * dw_apb_clocksource_register() - register the APB clocksource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)  * @dw_cs:	The clocksource to register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) void dw_apb_clocksource_register(struct dw_apb_clocksource *dw_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	clocksource_register_hz(&dw_cs->cs, dw_cs->timer.freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)  * dw_apb_clocksource_read() - read the current value of a clocksource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)  * @dw_cs:	The clocksource to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u64 dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	return (u64)~apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }