Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) ST-Ericsson SA 2011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Author: Sundar Iyer for ST-Ericsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * sched_clock implementation is based on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * DBx500-PRCMU Timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * The PRCMU has 5 timers which are available in a always-on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * power domain.  We use the Timer 4 for our always-on clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * source on DB8500.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RATE_32K		32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TIMER_MODE_CONTINOUS	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TIMER_DOWNCOUNT_VAL	0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PRCMU_TIMER_REF		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PRCMU_TIMER_DOWNCOUNT	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PRCMU_TIMER_MODE	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void __iomem *clksrc_dbx500_timer_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static u64 notrace clksrc_dbx500_prcmu_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	void __iomem *base = clksrc_dbx500_timer_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	u32 count, count2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		count = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		count2 = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	} while (count2 != count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	/* Negate because the timer is a decrementing counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	return ~count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct clocksource clocksource_dbx500_prcmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	.name		= "dbx500-prcmu-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	.rating		= 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	.read		= clksrc_dbx500_prcmu_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	.mask		= CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int __init clksrc_dbx500_prcmu_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	clksrc_dbx500_timer_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	 * The A9 sub system expects the timer to be configured as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	 * a continous looping timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	 * The PRCMU should configure it but if it for some reason
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	 * don't we do it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	    TIMER_MODE_CONTINOUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		writel(TIMER_MODE_CONTINOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		       clksrc_dbx500_timer_base + PRCMU_TIMER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		writel(TIMER_DOWNCOUNT_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		       clksrc_dbx500_timer_base + PRCMU_TIMER_REF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	return clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) TIMER_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 		       clksrc_dbx500_prcmu_init);