^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DRIVER_NAME "asm9260-timer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * this device provide 4 offsets for each register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 0x0 - plain read write mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * 0x4 - set mode, OR logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * 0x8 - clr mode, XOR logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 0xc - togle mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SET_REG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLR_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HW_IR 0x0000 /* RW. Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BM_IR_CR0 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BM_IR_MR3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BM_IR_MR2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BM_IR_MR1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BM_IR_MR0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HW_TCR 0x0010 /* RW. Timer controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* BM_C*_RST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Timer Counter and the Prescale Counter are synchronously reset on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * next positive edge of PCLK. The counters remain reset until TCR[1] is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * returned to zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BM_C3_RST BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BM_C2_RST BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BM_C1_RST BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BM_C0_RST BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* BM_C*_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * 1 - Timer Counter and Prescale Counter are enabled for counting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * 0 - counters are disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BM_C3_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BM_C2_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BM_C1_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BM_C0_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HW_DIR 0x0020 /* RW. Direction? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* 00 - count up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 01 - count down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 10 - ?? 2^n/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BM_DIR_COUNT_UP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BM_DIR_COUNT_DOWN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BM_DIR0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BM_DIR1_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BM_DIR2_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BM_DIR3_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BM_DIR_DEFAULT (BM_DIR_COUNT_UP << BM_DIR0_SHIFT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) BM_DIR_COUNT_UP << BM_DIR1_SHIFT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) BM_DIR_COUNT_UP << BM_DIR2_SHIFT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) BM_DIR_COUNT_UP << BM_DIR3_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HW_TC0 0x0030 /* RO. Timer counter 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* HW_TC*. Timer counter owerflow (0xffff.ffff to 0x0000.0000) do not generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * interrupt. This registers can be used to detect overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define HW_TC1 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define HW_TC2 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HW_TC3 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HW_PR 0x0070 /* RW. prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BM_PR_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HW_PC 0x0080 /* RO. Prescaler counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HW_MCR 0x0090 /* RW. Match control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* enable interrupt on match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BM_MCR_INT_EN(n) (1 << (n * 3 + 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* enable TC reset on match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BM_MCR_RES_EN(n) (1 << (n * 3 + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* enable stop TC on match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BM_MCR_STOP_EN(n) (1 << (n * 3 + 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HW_MR0 0x00a0 /* RW. Match reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HW_MR1 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HW_MR2 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HW_MR3 0x00D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HW_CTCR 0x0180 /* Counter control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define BM_CTCR0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BM_CTCR1_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BM_CTCR2_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BM_CTCR3_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define BM_CTCR_TM 0 /* Timer mode. Every rising PCLK edge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define BM_CTCR_DEFAULT (BM_CTCR_TM << BM_CTCR0_SHIFT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) BM_CTCR_TM << BM_CTCR1_SHIFT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) BM_CTCR_TM << BM_CTCR2_SHIFT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) BM_CTCR_TM << BM_CTCR3_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct asm9260_timer_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned long ticks_per_jiffy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int asm9260_timer_set_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* configure match count for TC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel_relaxed(delta, priv.base + HW_MR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* enable TC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline void __asm9260_timer_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* stop timer0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) writel_relaxed(BM_C0_EN, priv.base + HW_TCR + CLR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int asm9260_timer_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) __asm9260_timer_shutdown(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int asm9260_timer_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) __asm9260_timer_shutdown(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* enable reset and stop on match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) priv.base + HW_MCR + SET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int asm9260_timer_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) __asm9260_timer_shutdown(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* disable reset and stop on match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) priv.base + HW_MCR + CLR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* configure match count for TC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) writel_relaxed(priv.ticks_per_jiffy, priv.base + HW_MR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* enable TC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static struct clock_event_device event_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .rating = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .features = CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .set_next_event = asm9260_timer_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .set_state_shutdown = asm9260_timer_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .set_state_periodic = asm9260_timer_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .set_state_oneshot = asm9260_timer_set_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .tick_resume = asm9260_timer_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static irqreturn_t asm9260_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writel_relaxed(BM_IR_MR0, priv.base + HW_IR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Timer initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int __init asm9260_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) priv.base = of_io_request_and_map(np, 0, np->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (IS_ERR(priv.base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pr_err("%pOFn: unable to map resource\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return PTR_ERR(priv.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pr_err("Failed to get clk!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pr_err("Failed to enable clk!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ret = request_irq(irq, asm9260_timer_interrupt, IRQF_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) DRIVER_NAME, &event_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pr_err("Failed to setup irq!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* set all timers for count-up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) writel_relaxed(BM_DIR_DEFAULT, priv.base + HW_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* disable divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel_relaxed(BM_PR_DISABLE, priv.base + HW_PR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* make sure all timers use every rising PCLK edge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writel_relaxed(BM_CTCR_DEFAULT, priv.base + HW_CTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* enable interrupt for TC0 and clean setting for all other lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writel_relaxed(BM_MCR_INT_EN(0) , priv.base + HW_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) clocksource_mmio_init(priv.base + HW_TC1, DRIVER_NAME, rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 200, 32, clocksource_mmio_readl_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Seems like we can't use counter without match register even if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * actions for MR are disabled. So, set MR to max value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) writel_relaxed(0xffffffff, priv.base + HW_MR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* enable TC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) writel_relaxed(BM_C1_EN, priv.base + HW_TCR + SET_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) priv.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) event_dev.cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) clockevents_config_and_register(&event_dev, rate, 0x2c00, 0xfffffffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) TIMER_OF_DECLARE(asm9260_timer, "alphascale,asm9260-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) asm9260_timer_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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