Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) Maxime Coquelin 2015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SYST_CSR	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SYST_RVR	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SYST_CVR	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SYST_CALIB	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SYST_CSR_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SYSTICK_LOAD_RELOAD_MASK 0x00FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int __init system_timer_of_register(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	struct clk *clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		pr_warn("system-timer: invalid base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	ret = of_property_read_u32(np, "clock-frequency", &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 			ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			goto out_clk_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		if (!rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	writel_relaxed(SYSTICK_LOAD_RELOAD_MASK, base + SYST_RVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	writel_relaxed(SYST_CSR_ENABLE, base + SYST_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	ret = clocksource_mmio_init(base + SYST_CVR, "arm_system_timer", rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 			200, 24, clocksource_mmio_readl_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		pr_err("failed to init clocksource (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		if (clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 			goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 			goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	pr_info("ARM System timer initialized as clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) out_clk_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	pr_warn("ARM System timer register failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) TIMER_OF_DECLARE(arm_systick, "arm,armv7m-systick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 			system_timer_of_register);