Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * drivers/clocksource/arm_global_timer.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Stuart Menefy <stuart.menefy@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define GT_COUNTER0	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define GT_COUNTER1	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define GT_CONTROL	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define GT_CONTROL_TIMER_ENABLE		BIT(0)  /* this bit is NOT banked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define GT_CONTROL_COMP_ENABLE		BIT(1)	/* banked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define GT_CONTROL_IRQ_ENABLE		BIT(2)	/* banked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define GT_CONTROL_AUTO_INC		BIT(3)	/* banked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define GT_INT_STATUS	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define GT_INT_STATUS_EVENT_FLAG	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define GT_COMP0	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define GT_COMP1	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define GT_AUTO_INC	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * We are expecting to be clocked by the ARM peripheral clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * Note: it is assumed we are using a prescaler value of zero, so this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * the units for all operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static void __iomem *gt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static unsigned long gt_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static int gt_ppi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static struct clock_event_device __percpu *gt_evt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * To get the value from the Global Timer Counter register proceed as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * 1. Read the upper 32-bit timer counter register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * 2. Read the lower 32-bit timer counter register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * 3. Read the upper 32-bit timer counter register again. If the value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  *  different to the 32-bit upper value read previously, go back to step 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  *  Otherwise the 64-bit timer counter value is correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static u64 notrace _gt_counter_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	u64 counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u32 lower;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u32 upper, old_upper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	upper = readl_relaxed(gt_base + GT_COUNTER1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		old_upper = upper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		lower = readl_relaxed(gt_base + GT_COUNTER0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		upper = readl_relaxed(gt_base + GT_COUNTER1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	} while (upper != old_upper);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	counter = upper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	counter <<= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	counter |= lower;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	return counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static u64 gt_counter_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	return _gt_counter_read();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * To ensure that updates to comparator value register do not set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * Interrupt Status Register proceed as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * 1. Clear the Comp Enable bit in the Timer Control Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * 2. Write the lower 32-bit Comparator Value Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * 3. Write the upper 32-bit Comparator Value Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static void gt_compare_set(unsigned long delta, int periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u64 counter = gt_counter_read();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	unsigned long ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	counter += delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	ctrl = GT_CONTROL_TIMER_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	writel_relaxed(ctrl, gt_base + GT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	writel_relaxed(lower_32_bits(counter), gt_base + GT_COMP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	writel_relaxed(upper_32_bits(counter), gt_base + GT_COMP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (periodic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		writel_relaxed(delta, gt_base + GT_AUTO_INC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		ctrl |= GT_CONTROL_AUTO_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	writel_relaxed(ctrl, gt_base + GT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int gt_clockevent_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	unsigned long ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	ctrl = readl(gt_base + GT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		  GT_CONTROL_AUTO_INC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	writel(ctrl, gt_base + GT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int gt_clockevent_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	gt_compare_set(DIV_ROUND_CLOSEST(gt_clk_rate, HZ), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int gt_clockevent_set_next_event(unsigned long evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 					struct clock_event_device *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	gt_compare_set(evt, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct clock_event_device *evt = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (!(readl_relaxed(gt_base + GT_INT_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 				GT_INT_STATUS_EVENT_FLAG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	 * ERRATA 740657( Global Timer can send 2 interrupts for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	 * the same event in single-shot mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 * Workaround:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	 *	Either disable single-shot mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	 *	Or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	 *	Modify the Interrupt Handler to avoid the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 *	offending sequence. This is achieved by clearing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 *	the Global Timer flag _after_ having incremented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	 *	the Comparator register	value to a higher value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (clockevent_state_oneshot(evt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		gt_compare_set(ULONG_MAX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int gt_starting_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct clock_event_device *clk = this_cpu_ptr(gt_evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	clk->name = "arm_global_timer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		CLOCK_EVT_FEAT_PERCPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	clk->set_state_shutdown = gt_clockevent_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	clk->set_state_periodic = gt_clockevent_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	clk->set_state_oneshot = gt_clockevent_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	clk->set_state_oneshot_stopped = gt_clockevent_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	clk->set_next_event = gt_clockevent_set_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	clk->cpumask = cpumask_of(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	clk->rating = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	clk->irq = gt_ppi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	clockevents_config_and_register(clk, gt_clk_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 					1, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int gt_dying_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct clock_event_device *clk = this_cpu_ptr(gt_evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	gt_clockevent_shutdown(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	disable_percpu_irq(clk->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static u64 gt_clocksource_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	return gt_counter_read();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void gt_resume(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	unsigned long ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	ctrl = readl(gt_base + GT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (!(ctrl & GT_CONTROL_TIMER_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		/* re-enable timer on resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static struct clocksource gt_clocksource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.name	= "arm_global_timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.rating	= 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.read	= gt_clocksource_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.mask	= CLOCKSOURCE_MASK(64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.resume = gt_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static u64 notrace gt_sched_clock_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	return _gt_counter_read();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static unsigned long gt_read_long(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	return readl_relaxed(gt_base + GT_COUNTER0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static struct delay_timer gt_delay_timer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.read_current_timer = gt_read_long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void __init gt_delay_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	gt_delay_timer.freq = gt_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	register_current_timer_delay(&gt_delay_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int __init gt_clocksource_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	writel(0, gt_base + GT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	writel(0, gt_base + GT_COUNTER0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	writel(0, gt_base + GT_COUNTER1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	/* enables timer on all the cores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	sched_clock_register(gt_sched_clock_read, 64, gt_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	return clocksource_register_hz(&gt_clocksource, gt_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int __init global_timer_of_register(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	struct clk *gt_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	 * In A9 r2p0 the comparators for each processor with the global timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	 * fire when the timer value is greater than or equal to. In previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	 * revisions the comparators fired when the timer value was equal to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	    && (read_cpuid_id() & 0xf0000f) < 0x200000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		pr_warn("global-timer: non support for this cpu version.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	gt_ppi = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (!gt_ppi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		pr_warn("global-timer: unable to parse irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	gt_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (!gt_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		pr_warn("global-timer: invalid base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	gt_clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (!IS_ERR(gt_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		err = clk_prepare_enable(gt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		pr_warn("global-timer: clk not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	gt_clk_rate = clk_get_rate(gt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	gt_evt = alloc_percpu(struct clock_event_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (!gt_evt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		pr_warn("global-timer: can't allocate memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 				 "gt", gt_evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		pr_warn("global-timer: can't register interrupt %d (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			gt_ppi, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	/* Register and immediately configure the timer on the boot CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	err = gt_clocksource_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		goto out_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	err = cpuhp_setup_state(CPUHP_AP_ARM_GLOBAL_TIMER_STARTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 				"clockevents/arm/global_timer:starting",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 				gt_starting_cpu, gt_dying_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		goto out_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	gt_delay_timer_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) out_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	free_percpu_irq(gt_ppi, gt_evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	free_percpu(gt_evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) out_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	clk_disable_unprepare(gt_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	iounmap(gt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	WARN(err, "ARM Global timer register failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Only tested on r2p2 and r3p0  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) TIMER_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			global_timer_of_register);