Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * programmed to go from @count to @limit and optionally interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * We've designated TIMER0 for clockevents and TIMER1 for clocksource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * which are suitable for UP and SMP based clocksources respectively
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <soc/arc/timers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <soc/arc/mcip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static unsigned long arc_timer_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static int noinline arc_get_timer_clk(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	clk = of_clk_get(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		pr_err("timer missing clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		pr_err("Couldn't enable parent clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	arc_timer_freq = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /********** Clock Source Device *********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #ifdef CONFIG_ARC_TIMERS_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static u64 arc_read_gfrc(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u32 l, h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	 * From a programming model pov, there seems to be just one instance of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	 * MCIP_CMD/MCIP_READBACK however micro-architecturally there's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	 * an instance PER ARC CORE (not per cluster), and there are dedicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	 * hardware decode logic (per core) inside ARConnect to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	 * simultaneous read/write accesses from cores via those two registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	 * So several concurrent commands to ARConnect are OK if they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	 * trying to access two different sub-components (like GFRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 * inter-core interrupt, etc...). HW also supports simultaneously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 * accessing GFRC by multiple cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 * That's why it is safe to disable hard interrupts on the local CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	 * before access to GFRC instead of taking global MCIP spinlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 * defined in arch/arc/kernel/mcip.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	__mcip_cmd(CMD_GFRC_READ_LO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	l = read_aux_reg(ARC_REG_MCIP_READBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	__mcip_cmd(CMD_GFRC_READ_HI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	h = read_aux_reg(ARC_REG_MCIP_READBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	return (((u64)h) << 32) | l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static notrace u64 arc_gfrc_clock_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	return arc_read_gfrc(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static struct clocksource arc_counter_gfrc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.name   = "ARConnect GFRC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.rating = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.read   = arc_read_gfrc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.mask   = CLOCKSOURCE_MASK(64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int __init arc_cs_setup_gfrc(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct mcip_bcr mp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	READ_BCR(ARC_REG_MCIP_BCR, mp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (!mp.gfrc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		pr_warn("Global-64-bit-Ctr clocksource not detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	ret = arc_get_timer_clk(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	sched_clock_register(arc_gfrc_clock_read, 64, arc_timer_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) TIMER_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AUX_RTC_CTRL	0x103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AUX_RTC_LOW	0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AUX_RTC_HIGH	0x105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static u64 arc_read_rtc(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u32 l, h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	 * hardware has an internal state machine which tracks readout of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 * low/high and updates the CTRL.status if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	 *  - interrupt/exception taken between the two reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	 *  - high increments after low has been read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		l = read_aux_reg(AUX_RTC_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		h = read_aux_reg(AUX_RTC_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		status = read_aux_reg(AUX_RTC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	} while (!(status & BIT(31)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	return (((u64)h) << 32) | l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static notrace u64 arc_rtc_clock_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return arc_read_rtc(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct clocksource arc_counter_rtc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.name   = "ARCv2 RTC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.rating = 350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.read   = arc_read_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.mask   = CLOCKSOURCE_MASK(64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int __init arc_cs_setup_rtc(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct bcr_timer timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	READ_BCR(ARC_REG_TIMERS_BCR, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (!timer.rtc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		pr_warn("Local-64-bit-Ctr clocksource not detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* Local to CPU hence not usable in SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (IS_ENABLED(CONFIG_SMP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		pr_warn("Local-64-bit-Ctr not usable in SMP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	ret = arc_get_timer_clk(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	write_aux_reg(AUX_RTC_CTRL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	sched_clock_register(arc_rtc_clock_read, 64, arc_timer_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) TIMER_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * 32bit TIMER1 to keep counting monotonically and wraparound
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static u64 arc_read_timer1(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	return (u64) read_aux_reg(ARC_REG_TIMER1_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static notrace u64 arc_timer1_clock_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return arc_read_timer1(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static struct clocksource arc_counter_timer1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.name   = "ARC Timer1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.rating = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.read   = arc_read_timer1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.mask   = CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int __init arc_cs_setup_timer1(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	/* Local to CPU hence not usable in SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (IS_ENABLED(CONFIG_SMP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	ret = arc_get_timer_clk(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	write_aux_reg(ARC_REG_TIMER1_CNT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	sched_clock_register(arc_timer1_clock_read, 32, arc_timer_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /********** Clock Event Device *********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int arc_timer_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  * Arm the timer to interrupt after @cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  * The distinction for oneshot/periodic is done in arc_event_timer_ack() below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void arc_timer_event_setup(unsigned int cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	write_aux_reg(ARC_REG_TIMER0_CNT, 0);	/* start from 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int arc_clkevent_set_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 				       struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	arc_timer_event_setup(delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int arc_clkevent_set_periodic(struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	 * At X Hz, 1 sec = 1000ms -> X cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	 *		      10ms -> X / 100 cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	arc_timer_event_setup(arc_timer_freq / HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.name			= "ARC Timer0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.features		= CLOCK_EVT_FEAT_ONESHOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 				  CLOCK_EVT_FEAT_PERIODIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.rating			= 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	.set_next_event		= arc_clkevent_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.set_state_periodic	= arc_clkevent_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static irqreturn_t timer_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	 * Note that generic IRQ core could have passed @evt for @dev_id if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	 * irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	int irq_reenable = clockevent_state_periodic(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	 * 1. ACK the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	 *    - For ARC700, any write to CTRL reg ACKs it, so just rewrite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	 *      Count when [N]ot [H]alted bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	 *    - For HS3x, it is a bit subtle. On taken count-down interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	 *      IP bit [3] is set, which needs to be cleared for ACK'ing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	 *      The write below can only update the other two bits, hence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	 *      explicitly clears IP bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	 * 2. Re-arm interrupt if periodic by writing to IE bit [0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int arc_timer_starting_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	evt->cpumask = cpumask_of(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	enable_percpu_irq(arc_timer_irq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int arc_timer_dying_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	disable_percpu_irq(arc_timer_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)  * clockevent setup for boot CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int __init arc_clockevent_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	arc_timer_irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (arc_timer_irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		pr_err("clockevent: missing irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	ret = arc_get_timer_clk(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	/* Needs apriori irq_set_percpu_devid() done in intc map function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	ret = request_percpu_irq(arc_timer_irq, timer_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 				 "Timer0 (per-cpu-tick)", evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		pr_err("clockevent: unable to request irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 				"clockevents/arc/timer:starting",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 				arc_timer_starting_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 				arc_timer_dying_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		pr_err("Failed to setup hotplug state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int __init arc_of_timer_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	static int init_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	if (!init_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		init_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		ret = arc_clockevent_setup(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		ret = arc_cs_setup_timer1(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) TIMER_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);