^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Zynq UltraScale+ MPSoC mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016-2018 Xilinx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-zynqmp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * DOC: basic adjustable multiplexer clock that cannot gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Traits of this clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * prepare - clk_prepare only ensures that parents are prepared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * enable - clk_enable only ensures that parents are enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * rate - rate is only affected by parent switching. No clk_set_rate support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * parent - parent is adjustable through clk_set_parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * struct zynqmp_clk_mux - multiplexer clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @hw: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @flags: hardware-specific flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @clk_id: Id of clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct zynqmp_clk_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define to_zynqmp_clk_mux(_hw) container_of(_hw, struct zynqmp_clk_mux, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * zynqmp_clk_mux_get_parent() - Get parent of clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * @hw: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Return: Parent index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static u8 zynqmp_clk_mux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const char *clk_name = clk_hw_get_name(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 clk_id = mux->clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ret = zynqmp_pm_clock_getparent(clk_id, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pr_warn_once("%s() getparent failed for clock: %s, ret = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) __func__, clk_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * zynqmp_clk_mux_set_parent() - Set parent of clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @hw: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @index: Parent index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Return: 0 on success else error+reason
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const char *clk_name = clk_hw_get_name(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 clk_id = mux->clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ret = zynqmp_pm_clock_setparent(clk_id, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pr_warn_once("%s() set parent failed for clock: %s, ret = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __func__, clk_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct clk_ops zynqmp_clk_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .get_parent = zynqmp_clk_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .set_parent = zynqmp_clk_mux_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .determine_rate = __clk_mux_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct clk_ops zynqmp_clk_mux_ro_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .get_parent = zynqmp_clk_mux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * zynqmp_clk_register_mux() - Register a mux table with the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @name: Name of this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @clk_id: Id of this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @parents: Name of this clock's parents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @num_parents: Number of parents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @nodes: Clock topology node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Return: clock hardware of the registered clock mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) const char * const *parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) const struct clock_topology *nodes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct zynqmp_clk_mux *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mux = kzalloc(sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (nodes->type_flag & CLK_MUX_READ_ONLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) init.ops = &zynqmp_clk_mux_ro_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) init.ops = &zynqmp_clk_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) init.flags = nodes->flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) init.parent_names = parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mux->flags = nodes->type_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) mux->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mux->clk_id = clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) hw = &mux->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) kfree(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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