^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Zynq UltraScale+ MPSoC clock controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016-2018 Xilinx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Gated clock implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "clk-zynqmp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * struct clk_gate - gating clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * @hw: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * @flags: hardware-specific flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * @clk_id: Id of clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct zynqmp_clk_gate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define to_zynqmp_clk_gate(_hw) container_of(_hw, struct zynqmp_clk_gate, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * zynqmp_clk_gate_enable() - Enable clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @hw: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Return: 0 on success else error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int zynqmp_clk_gate_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) const char *clk_name = clk_hw_get_name(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 clk_id = gate->clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ret = zynqmp_pm_clock_enable(clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) pr_warn_once("%s() clock enabled failed for %s, ret = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __func__, clk_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * zynqmp_clk_gate_disable() - Disable clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @hw: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void zynqmp_clk_gate_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const char *clk_name = clk_hw_get_name(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 clk_id = gate->clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ret = zynqmp_pm_clock_disable(clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pr_warn_once("%s() clock disable failed for %s, ret = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __func__, clk_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * zynqmp_clk_gate_is_enable() - Check clock state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @hw: handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Return: 1 if enabled, 0 if disabled else error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int zynqmp_clk_gate_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) const char *clk_name = clk_hw_get_name(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 clk_id = gate->clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int state, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ret = zynqmp_pm_clock_getstate(clk_id, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __func__, clk_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return state ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const struct clk_ops zynqmp_clk_gate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .enable = zynqmp_clk_gate_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .disable = zynqmp_clk_gate_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .is_enabled = zynqmp_clk_gate_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * zynqmp_clk_register_gate() - Register a gate clock with the clock framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @name: Name of this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @clk_id: Id of this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @parents: Name of this clock's parents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @num_parents: Number of parents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @nodes: Clock topology node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Return: clock hardware of the registered clock gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const char * const *parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) const struct clock_topology *nodes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct zynqmp_clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* allocate the gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) init.ops = &zynqmp_clk_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) init.flags = nodes->flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) init.parent_names = parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* struct clk_gate assignments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) gate->flags = nodes->type_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) gate->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) gate->clk_id = clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) hw = &gate->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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