^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Zynq PLL driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Xilinx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Sören Brinkmann <soren.brinkmann@xilinx.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk/zynq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * struct zynq_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * @hw: Handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * @pll_ctrl: PLL control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * @pll_status: PLL status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * @lock: Register lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * @lockbit: Indicates the associated PLL_LOCKED bit in the PLL status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct zynq_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) void __iomem *pll_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) void __iomem *pll_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 lockbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define to_zynq_pll(_hw) container_of(_hw, struct zynq_pll, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Register bitfield defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PLLCTRL_FBDIV_MASK 0x7f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PLLCTRL_FBDIV_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PLLCTRL_BPQUAL_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PLLCTRL_PWRDWN_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PLLCTRL_PWRDWN_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PLLCTRL_RESET_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PLLCTRL_RESET_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PLL_FBDIV_MIN 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PLL_FBDIV_MAX 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * zynq_pll_round_rate() - Round a clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @hw: Handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @rate: Desired clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @prate: Clock frequency of parent clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Returns frequency closest to @rate the hardware can generate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (fbdiv < PLL_FBDIV_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) fbdiv = PLL_FBDIV_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) else if (fbdiv > PLL_FBDIV_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) fbdiv = PLL_FBDIV_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return *prate * fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * zynq_pll_recalc_rate() - Recalculate clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @hw: Handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @parent_rate: Clock frequency of parent clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Returns current clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct zynq_pll *clk = to_zynq_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * makes probably sense to redundantly save fbdiv in the struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * zynq_pll to save the IO access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PLLCTRL_FBDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return parent_rate * fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * zynq_pll_is_enabled - Check if a clock is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @hw: Handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Returns 1 if the clock is enabled, 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Not sure this is a good idea, but since disabled means bypassed for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * this clock implementation we say we are always enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int zynq_pll_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct zynq_pll *clk = to_zynq_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) spin_lock_irqsave(clk->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) reg = readl(clk->pll_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) spin_unlock_irqrestore(clk->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return !(reg & (PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * zynq_pll_enable - Enable clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @hw: Handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Returns 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int zynq_pll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct zynq_pll *clk = to_zynq_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (zynq_pll_is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pr_info("PLL: enable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Power up PLL and wait for lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) spin_lock_irqsave(clk->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) reg = readl(clk->pll_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writel(reg, clk->pll_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) while (!(readl(clk->pll_status) & (1 << clk->lockbit)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) spin_unlock_irqrestore(clk->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * zynq_pll_disable - Disable clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @hw: Handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Returns 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void zynq_pll_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct zynq_pll *clk = to_zynq_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (!zynq_pll_is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pr_info("PLL: shutdown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* shut down PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) spin_lock_irqsave(clk->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) reg = readl(clk->pll_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) writel(reg, clk->pll_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) spin_unlock_irqrestore(clk->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct clk_ops zynq_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .enable = zynq_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .disable = zynq_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .is_enabled = zynq_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .round_rate = zynq_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .recalc_rate = zynq_pll_recalc_rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * clk_register_zynq_pll() - Register PLL with the clock framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @name PLL name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @parent Parent clock name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @pll_ctrl Pointer to PLL control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @pll_status Pointer to PLL status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @lock_index Bit index to this PLL's lock status bit in @pll_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @lock Register lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Returns handle to the registered clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct clk *clk_register_zynq_pll(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct zynq_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) const char *parent_arr[1] = {parent};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct clk_init_data initd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .name = name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .parent_names = parent_arr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .ops = &zynq_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .flags = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pll = kmalloc(sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Populate the struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pll->hw.init = &initd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pll->pll_ctrl = pll_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pll->pll_status = pll_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pll->lockbit = lock_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pll->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) spin_lock_irqsave(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) reg = readl(pll->pll_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) reg &= ~PLLCTRL_BPQUAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) writel(reg, pll->pll_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) spin_unlock_irqrestore(pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) clk = clk_register(NULL, &pll->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (WARN_ON(IS_ERR(clk)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) goto free_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) free_pll:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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