^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Zynq clock controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 - 2013 Xilinx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Sören Brinkmann <soren.brinkmann@xilinx.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk/zynq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static void __iomem *zynq_clkc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SLCR_ARMPLL_CTRL (zynq_clkc_base + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SLCR_DDRPLL_CTRL (zynq_clkc_base + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SLCR_IOPLL_CTRL (zynq_clkc_base + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SLCR_PLL_STATUS (zynq_clkc_base + 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SLCR_ARM_CLK_CTRL (zynq_clkc_base + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SLCR_DDR_CLK_CTRL (zynq_clkc_base + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SLCR_DCI_CLK_CTRL (zynq_clkc_base + 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SLCR_APER_CLK_CTRL (zynq_clkc_base + 0x2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SLCR_GEM0_CLK_CTRL (zynq_clkc_base + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SLCR_GEM1_CLK_CTRL (zynq_clkc_base + 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SLCR_SMC_CLK_CTRL (zynq_clkc_base + 0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SLCR_LQSPI_CLK_CTRL (zynq_clkc_base + 0x4c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SLCR_SDIO_CLK_CTRL (zynq_clkc_base + 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SLCR_UART_CLK_CTRL (zynq_clkc_base + 0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SLCR_SPI_CLK_CTRL (zynq_clkc_base + 0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SLCR_CAN_CLK_CTRL (zynq_clkc_base + 0x5c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SLCR_CAN_MIOCLK_CTRL (zynq_clkc_base + 0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SLCR_DBG_CLK_CTRL (zynq_clkc_base + 0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SLCR_PCAP_CLK_CTRL (zynq_clkc_base + 0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SLCR_FPGA0_CLK_CTRL (zynq_clkc_base + 0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SLCR_621_TRUE (zynq_clkc_base + 0xc4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SLCR_SWDT_CLK_SEL (zynq_clkc_base + 0x204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NUM_MIO_PINS 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DBG_CLK_CTRL_CLKACT_TRC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DBG_CLK_CTRL_CPU_1XCLKACT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) enum zynq_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) armpll, ddrpll, iopll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ddr2x, ddr3x, dci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) sdio0, sdio1, uart0, uart1, spi0, spi1, dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) usb0_aper, usb1_aper, gem0_aper, gem1_aper,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) smc_aper, swdt, dbg_trc, dbg_apb, clk_max};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct clk *ps_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct clk *clks[clk_max];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct clk_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static DEFINE_SPINLOCK(armpll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static DEFINE_SPINLOCK(ddrpll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static DEFINE_SPINLOCK(iopll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static DEFINE_SPINLOCK(armclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static DEFINE_SPINLOCK(swdtclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static DEFINE_SPINLOCK(ddrclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static DEFINE_SPINLOCK(dciclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static DEFINE_SPINLOCK(gem0clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static DEFINE_SPINLOCK(gem1clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static DEFINE_SPINLOCK(canclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static DEFINE_SPINLOCK(canmioclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static DEFINE_SPINLOCK(dbgclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static DEFINE_SPINLOCK(aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static const char *const armpll_parents[] __initconst = {"armpll_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "ps_clk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const char *const ddrpll_parents[] __initconst = {"ddrpll_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "ps_clk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const char *const iopll_parents[] __initconst = {"iopll_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "ps_clk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const char *gem0_mux_parents[] __initdata = {"gem0_div1", "dummy_name"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const char *gem1_mux_parents[] __initdata = {"gem1_div1", "dummy_name"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const char *const can0_mio_mux2_parents[] __initconst = {"can0_gate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "can0_mio_mux"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const char *const can1_mio_mux2_parents[] __initconst = {"can1_gate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "can1_mio_mux"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "dummy_name"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const char *const dbgtrc_emio_input_names[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "trace_emio_clk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const char *const gem0_emio_input_names[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "gem0_emio_clk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const char *const gem1_emio_input_names[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "gem1_emio_clk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const char *const swdt_ext_clk_input_names[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "swdt_ext_clk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const char *clk_name, void __iomem *fclk_ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) const char **parents, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) char *mux_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) char *div0_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) char *div1_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) spinlock_t *fclk_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) spinlock_t *fclk_gate_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (!fclk_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!fclk_gate_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) goto err_fclk_gate_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) spin_lock_init(fclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) spin_lock_init(fclk_gate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!mux_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) goto err_mux_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (!div0_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) goto err_div0_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!div1_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) goto err_div1_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) clk = clk_register_mux(NULL, mux_name, parents, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) fclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clk = clk_register_divider(NULL, div0_name, mux_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) clk = clk_register_divider(NULL, div1_name, div0_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) fclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) clks[fclk] = clk_register_gate(NULL, clk_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) enable_reg = readl(fclk_gate_reg) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (enable && !enable_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (clk_prepare_enable(clks[fclk]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) pr_warn("%s: FCLK%u enable failed\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) fclk - fclk0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) kfree(mux_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) kfree(div0_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) kfree(div1_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) err_div1_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) kfree(div0_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) err_div0_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) kfree(mux_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) err_mux_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) kfree(fclk_gate_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) err_fclk_gate_lock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) kfree(fclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) clks[fclk] = ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) enum zynq_clk clk1, const char *clk_name0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) const char *clk_name1, void __iomem *clk_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) const char **parents, unsigned int two_gates)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) char *mux_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) char *div_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) lock = kmalloc(sizeof(*lock), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) spin_lock_init(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) clk = clk_register_mux(NULL, mux_name, parents, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (two_gates)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) kfree(mux_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) kfree(div_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clks[clk0] = ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (two_gates)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) clks[clk1] = ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static void __init zynq_clk_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) char *clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int fclk_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) const char *clk_output_name[clk_max];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) const char *cpu_parents[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) const char *periph_parents[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) const char *swdt_ext_clk_mux_parents[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) const char *can_mio_mux_parents[NUM_MIO_PINS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) const char *dummy_nm = "dummy_name";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pr_info("Zynq clock init\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* get clock output names from DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) for (i = 0; i < clk_max; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (of_property_read_string_index(np, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) i, &clk_output_name[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pr_err("%s: clock output name not in DT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) cpu_parents[0] = clk_output_name[armpll];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) cpu_parents[1] = clk_output_name[armpll];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) cpu_parents[2] = clk_output_name[ddrpll];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) cpu_parents[3] = clk_output_name[iopll];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) periph_parents[0] = clk_output_name[iopll];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) periph_parents[1] = clk_output_name[iopll];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) periph_parents[2] = clk_output_name[armpll];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) periph_parents[3] = clk_output_name[ddrpll];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) of_property_read_u32(np, "fclk-enable", &fclk_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* ps_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) tmp = 33333333;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, 0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) SLCR_PLL_STATUS, 0, &armpll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) SLCR_PLL_STATUS, 1, &ddrpll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) SLCR_PLL_STATUS, 2, &iopll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* CPU clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) tmp = readl(SLCR_621_TRUE) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) &armclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "cpu_3or2x_div", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 2 + tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 26, 0, &armclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) clk_prepare_enable(clks[cpu_2x]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 4 + 2 * tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 0, &armclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int idx = of_property_match_string(np, "clock-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) swdt_ext_clk_input_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) swdt_ext_clk_mux_parents[i + 1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) of_clk_get_parent_name(np, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) &swdtclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* DDR clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) clk_prepare_enable(clks[ddr2x]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) clk_prepare_enable(clks[ddr3x]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) &dciclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) &dciclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) clk_prepare_enable(clks[dci]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Peripheral clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) for (i = fclk0; i <= fclk3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int enable = !!(fclk_enable & BIT(i - fclk0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) zynq_clk_register_fclk(i, clk_output_name[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) periph_parents, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) SLCR_SMC_CLK_CTRL, periph_parents, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) SLCR_PCAP_CLK_CTRL, periph_parents, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) periph_parents, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) clk_output_name[uart1], SLCR_UART_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) periph_parents, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) clk_output_name[spi1], SLCR_SPI_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) periph_parents, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int idx = of_property_match_string(np, "clock-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) gem0_emio_input_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) &gem0clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) &gem0clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) SLCR_GEM0_CLK_CTRL, 6, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) &gem0clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "gem0_emio_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int idx = of_property_match_string(np, "clock-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) gem1_emio_input_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) &gem1clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) &gem1clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) SLCR_GEM1_CLK_CTRL, 6, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) &gem1clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "gem1_emio_mux", CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) tmp = strlen("mio_clk_00x");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) clk_name = kmalloc(tmp, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) for (i = 0; i < NUM_MIO_PINS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) snprintf(clk_name, tmp, "mio_clk_%2.2d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) idx = of_property_match_string(np, "clock-names", clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) can_mio_mux_parents[i] = of_clk_get_parent_name(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) can_mio_mux_parents[i] = dummy_nm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) kfree(clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) &canclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) clk = clk_register_divider(NULL, "can_div1", "can_div0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) &canclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) clk = clk_register_gate(NULL, "can0_gate", "can_div1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) &canclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) clk = clk_register_gate(NULL, "can1_gate", "can_div1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) &canclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) clk = clk_register_mux(NULL, "can0_mio_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) &canmioclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) clk = clk_register_mux(NULL, "can1_mio_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 0, &canmioclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) &canmioclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 0, &canmioclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) int idx = of_property_match_string(np, "clock-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dbgtrc_emio_input_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) &dbgclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) &dbgclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 0, 0, &dbgclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) &dbgclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* leave debug clocks in the state the bootloader set them up to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) tmp = readl(SLCR_DBG_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (tmp & DBG_CLK_CTRL_CLKACT_TRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (clk_prepare_enable(clks[dbg_trc]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) pr_warn("%s: trace clk enable failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (clk_prepare_enable(clks[dbg_apb]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pr_warn("%s: debug APB clk enable failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* One gated clock for all APER clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) clks[dma] = clk_register_gate(NULL, clk_output_name[dma],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) &aperclk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) for (i = 0; i < ARRAY_SIZE(clks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (IS_ERR(clks[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) pr_err("Zynq clk %d: register failed with %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) i, PTR_ERR(clks[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) clk_data.clks = clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) clk_data.clk_num = ARRAY_SIZE(clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) void __init zynq_clock_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct device_node *slcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) pr_err("%s: clkc node not found\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) goto np_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (of_address_to_resource(np, 0, &res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pr_err("%pOFn: failed to get resource\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) goto np_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) slcr = of_get_parent(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (slcr->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) zynq_clkc_base = (__force void __iomem *)slcr->data + res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) pr_err("%pOFn: Unable to get I/O memory\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) of_node_put(slcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) goto np_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) of_node_put(slcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) np_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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