^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2015 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 ZTE Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __ZTE_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __ZTE_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PNAME(x) static const char *x[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct zx_pll_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u32 cfg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u32 cfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct clk_zx_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) const struct zx_pll_config *lookup_table; /* order by rate asc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u8 pd_bit; /* power down bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u8 lock_bit; /* pll lock flag bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PLL_RATE(_rate, _cfg0, _cfg1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .rate = _rate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .cfg0 = _cfg0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .cfg1 = _cfg1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .reg_base = (void __iomem *) _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .lookup_table = _table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .count = ARRAY_SIZE(_table), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .pd_bit = _pd, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .lock_bit = _lock, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .hw.init = CLK_HW_INIT(_name, _parent, &zx_pll_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) CLK_GET_RATE_NOCACHE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * The pd_bit is not available on ZX296718, so let's pass something
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * bigger than 31, e.g. 0xff, to indicate that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ZX296718_PLL(_name, _parent, _reg, _table) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct zx_clk_gate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct clk_gate gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .gate = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .reg = (void __iomem *) _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .bit_idx = (_bit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .flags = _gflags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .lock = &clk_lock, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .hw.init = CLK_HW_INIT(_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) &clk_gate_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) _flag | CLK_IGNORE_UNUSED), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct zx_clk_fixed_factor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct clk_fixed_factor factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .factor = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .div = _div, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .mult = _mult, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .hw.init = CLK_HW_INIT(_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) &clk_fixed_factor_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) _flag), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct zx_clk_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct clk_mux mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .mux = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .reg = (void __iomem *) _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .mask = BIT(_width) - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .flags = _mflag, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .lock = &clk_lock, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .hw.init = CLK_HW_INIT_PARENTS(_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) &clk_mux_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) _flag), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MUX(_id, _name, _parent, _reg, _shift, _width) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct zx_clk_div {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct clk_divider div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .div = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .reg = (void __iomem *) _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .flags = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .table = _table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .lock = &clk_lock, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .hw.init = CLK_HW_INIT(_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) &clk_divider_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) _flag), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct clk_zx_audio_divider {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int rate_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AUDIO_DIV(_id, _name, _parent, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .reg_base = (void __iomem *) _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .lock = &clk_lock, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .hw.init = CLK_HW_INIT(_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) &zx_audio_div_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned long flags, void __iomem *reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) const struct zx_pll_config *lookup_table, int count, spinlock_t *lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct clk_zx_audio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct clk *clk_register_zx_audio(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const char * const parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned long flags, void __iomem *reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) extern const struct clk_ops zx_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) extern const struct clk_ops zx_audio_div_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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