^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2014 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 ZTE Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define to_clk_zx_pll(_hw) container_of(_hw, struct clk_zx_pll, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define to_clk_zx_audio(_hw) container_of(_hw, struct clk_zx_audio, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CFG0_CFG1_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LOCK_FLAG 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define POWER_DOWN 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int rate_to_idx(struct clk_zx_pll *zx_pll, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) const struct zx_pll_config *config = zx_pll->lookup_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) for (i = 0; i < zx_pll->count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if (config[i].rate > rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) return i > 0 ? i - 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (config[i].rate == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return i - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int hw_to_idx(struct clk_zx_pll *zx_pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) const struct zx_pll_config *config = zx_pll->lookup_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 hw_cfg0, hw_cfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) hw_cfg0 = readl_relaxed(zx_pll->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) hw_cfg1 = readl_relaxed(zx_pll->reg_base + CFG0_CFG1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* For matching the value in lookup table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) hw_cfg0 &= ~BIT(zx_pll->lock_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Check availability of pd_bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (zx_pll->pd_bit < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) hw_cfg0 |= BIT(zx_pll->pd_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) for (i = 0; i < zx_pll->count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static unsigned long zx_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) idx = hw_to_idx(zx_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (unlikely(idx == -EINVAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return zx_pll->lookup_table[idx].rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static long zx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) idx = rate_to_idx(zx_pll, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return zx_pll->lookup_table[idx].rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int zx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Assume current cpu is not running on current PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const struct zx_pll_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) idx = rate_to_idx(zx_pll, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) config = &zx_pll->lookup_table[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) writel_relaxed(config->cfg0, zx_pll->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel_relaxed(config->cfg1, zx_pll->reg_base + CFG0_CFG1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int zx_pll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* If pd_bit is not available, simply return success. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (zx_pll->pd_bit > 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) reg = readl_relaxed(zx_pll->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return readl_relaxed_poll_timeout(zx_pll->reg_base, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) reg & BIT(zx_pll->lock_bit), 0, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void zx_pll_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (zx_pll->pd_bit > 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) reg = readl_relaxed(zx_pll->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int zx_pll_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) reg = readl_relaxed(zx_pll->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return !(reg & BIT(zx_pll->pd_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) const struct clk_ops zx_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .recalc_rate = zx_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .round_rate = zx_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .set_rate = zx_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .enable = zx_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .disable = zx_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .is_enabled = zx_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) EXPORT_SYMBOL(zx_pll_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned long flags, void __iomem *reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const struct zx_pll_config *lookup_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int count, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct clk_zx_pll *zx_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) zx_pll = kzalloc(sizeof(*zx_pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (!zx_pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) init.ops = &zx_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) init.parent_names = parent_name ? &parent_name : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) init.num_parents = parent_name ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) zx_pll->reg_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) zx_pll->lookup_table = lookup_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) zx_pll->count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) zx_pll->lock_bit = LOCK_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) zx_pll->pd_bit = POWER_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) zx_pll->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) zx_pll->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) clk = clk_register(NULL, &zx_pll->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) kfree(zx_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define BPAR 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static u32 calc_reg(u32 parent_rate, u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 sel, integ, fra_div, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u64 tmp64 = (u64)parent_rate * BPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) do_div(tmp64, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) integ = (u32)tmp64 / BPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) integ = integ >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) tmp = (u32)tmp64 % BPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) sel = tmp / BPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) tmp = tmp % BPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) fra_div = tmp * 0xff / BPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) tmp = (sel << 24) | (integ << 16) | (0xff << 8) | fra_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Set I2S integer divider as 1. This bit is reserved for SPDIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * and do no harm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) tmp |= BIT(28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static u32 calc_rate(u32 reg, u32 parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 sel, integ, fra_div, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u64 tmp64 = (u64)parent_rate * BPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tmp = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) sel = (tmp >> 24) & BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) integ = (tmp >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) fra_div = tmp & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) tmp = fra_div * BPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) tmp = tmp / 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) tmp += sel * BPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) tmp += 2 * integ * BPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) do_div(tmp64, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return (u32)tmp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static unsigned long zx_audio_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) reg = readl_relaxed(zx_audio->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return calc_rate(reg, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static long zx_audio_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (rate * 2 > *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) reg = calc_reg(*prate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return calc_rate(reg, *prate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int zx_audio_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) reg = calc_reg(parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) writel_relaxed(reg, zx_audio->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define ZX_AUDIO_EN BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int zx_audio_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) reg = readl_relaxed(zx_audio->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) writel_relaxed(reg & ~ZX_AUDIO_EN, zx_audio->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void zx_audio_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) reg = readl_relaxed(zx_audio->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) writel_relaxed(reg | ZX_AUDIO_EN, zx_audio->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct clk_ops zx_audio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .recalc_rate = zx_audio_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .round_rate = zx_audio_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .set_rate = zx_audio_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .enable = zx_audio_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .disable = zx_audio_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct clk *clk_register_zx_audio(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) const char * const parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) void __iomem *reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct clk_zx_audio *zx_audio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) zx_audio = kzalloc(sizeof(*zx_audio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!zx_audio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) init.ops = &zx_audio_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) init.parent_names = parent_name ? &parent_name : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) init.num_parents = parent_name ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) zx_audio->reg_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) zx_audio->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) clk = clk_register(NULL, &zx_audio->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) kfree(zx_audio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define CLK_AUDIO_DIV_FRAC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CLK_AUDIO_DIV_INT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CLK_AUDIO_DIV_UNCOMMON BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CLK_AUDIO_DIV_FRAC_NSHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define CLK_AUDIO_DIV_INT_FRAC_RE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CLK_AUDIO_DIV_INT_FRAC_MAX (0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CLK_AUDIO_DIV_INT_FRAC_MIN (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define CLK_AUDIO_DIV_INT_INT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CLK_AUDIO_DIV_INT_INT_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct zx_clk_audio_div_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned int int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned int frac_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define to_clk_zx_audio_div(_hw) container_of(_hw, struct clk_zx_audio_divider, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static unsigned long audio_calc_rate(struct clk_zx_audio_divider *audio_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 reg_frac, u32 reg_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned long rate, m, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) m = reg_frac & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) n = (reg_frac >> 16) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) m = (reg_int & 0xffff) * n + m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) rate = (parent_rate * n) / m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void audio_calc_reg(struct clk_zx_audio_divider *audio_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct zx_clk_audio_div_table *div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned long rate, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned int reg_int, reg_frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned long m, n, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) reg_int = parent_rate / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (reg_int > CLK_AUDIO_DIV_INT_FRAC_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) reg_int = CLK_AUDIO_DIV_INT_FRAC_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) else if (reg_int < CLK_AUDIO_DIV_INT_FRAC_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) reg_int = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) m = parent_rate - rate * reg_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) n = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) div = gcd(m, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) m = m / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) n = n / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if ((m >> 16) || (n >> 16)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (m > n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) n = n * 0xffff / m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) m = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) m = m * 0xffff / n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) n = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) reg_frac = m | (n << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) div_table->rate = parent_rate * n / (reg_int * n + m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) div_table->int_reg = reg_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) div_table->frac_reg = reg_frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static unsigned long zx_audio_div_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u32 reg_frac, reg_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) reg_frac = readl_relaxed(zx_audio_div->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) reg_int = readl_relaxed(zx_audio_div->reg_base + 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return audio_calc_rate(zx_audio_div, reg_frac, reg_int, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static long zx_audio_div_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct zx_clk_audio_div_table divt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) audio_calc_reg(zx_audio_div, &divt, rate, *prate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return audio_calc_rate(zx_audio_div, divt.frac_reg, divt.int_reg, *prate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int zx_audio_div_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct zx_clk_audio_div_table divt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) audio_calc_reg(zx_audio_div, &divt, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (divt.rate != rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pr_debug("the real rate is:%ld", divt.rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) writel_relaxed(divt.frac_reg, zx_audio_div->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) val = readl_relaxed(zx_audio_div->reg_base + 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) val &= ~0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) val |= divt.int_reg | CLK_AUDIO_DIV_INT_FRAC_RE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) writel_relaxed(val, zx_audio_div->reg_base + 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) val = readl_relaxed(zx_audio_div->reg_base + 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) val &= ~CLK_AUDIO_DIV_INT_FRAC_RE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) writel_relaxed(val, zx_audio_div->reg_base + 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) const struct clk_ops zx_audio_div_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .recalc_rate = zx_audio_div_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .round_rate = zx_audio_div_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .set_rate = zx_audio_div_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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