^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 - 2016 ZTE Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2016 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/zx296718-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* TOP CRM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TOP_CLK_MUX0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TOP_CLK_MUX1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TOP_CLK_MUX2 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TOP_CLK_MUX3 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TOP_CLK_MUX4 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TOP_CLK_MUX5 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TOP_CLK_MUX6 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TOP_CLK_MUX7 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TOP_CLK_MUX9 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TOP_CLK_GATE0 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TOP_CLK_GATE1 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TOP_CLK_GATE2 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TOP_CLK_GATE3 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TOP_CLK_GATE4 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TOP_CLK_GATE5 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TOP_CLK_GATE6 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TOP_CLK_DIV0 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PLL_CPU_REG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PLL_VGA_REG 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PLL_DDR_REG 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* LSP0 CRM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LSP0_TIMER3_CLK 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LSP0_TIMER4_CLK 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LSP0_TIMER5_CLK 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LSP0_UART3_CLK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LSP0_UART1_CLK 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LSP0_UART2_CLK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LSP0_SPIFC0_CLK 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LSP0_I2C4_CLK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LSP0_I2C5_CLK 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LSP0_SSP0_CLK 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LSP0_SSP1_CLK 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LSP0_USIM0_CLK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LSP0_GPIO_CLK 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LSP0_I2C3_CLK 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* LSP1 CRM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LSP1_UART4_CLK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LSP1_UART5_CLK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LSP1_PWM_CLK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LSP1_I2C2_CLK 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LSP1_SSP2_CLK 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LSP1_SSP3_CLK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LSP1_SSP4_CLK 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LSP1_USIM1_CLK 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* audio lsp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AUDIO_I2S0_DIV_CFG1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AUDIO_I2S0_DIV_CFG2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AUDIO_I2S0_CLK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AUDIO_I2S1_DIV_CFG1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AUDIO_I2S1_DIV_CFG2 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AUDIO_I2S1_CLK 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AUDIO_I2S2_DIV_CFG1 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AUDIO_I2S2_DIV_CFG2 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AUDIO_I2S2_CLK 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AUDIO_I2S3_DIV_CFG1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AUDIO_I2S3_DIV_CFG2 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AUDIO_I2S3_CLK 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AUDIO_I2C0_CLK 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AUDIO_SPDIF0_DIV_CFG1 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AUDIO_SPDIF0_DIV_CFG2 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AUDIO_SPDIF0_CLK 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AUDIO_SPDIF1_DIV_CFG1 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AUDIO_SPDIF1_DIV_CFG2 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AUDIO_SPDIF1_CLK 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AUDIO_TIMER_CLK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AUDIO_TDM_CLK 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AUDIO_TS_CLK 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static DEFINE_SPINLOCK(clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const struct zx_pll_config pll_cpu_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PLL_RATE(1312000000, 0x00103621, 0x04aaaaaa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PLL_RATE(1407000000, 0x00103a21, 0x04aaaaaa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PLL_RATE(1503000000, 0x00103e21, 0x04aaaaaa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PLL_RATE(1600000000, 0x00104221, 0x04aaaaaa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct zx_pll_config pll_vga_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PLL_RATE(36000000, 0x00102464, 0x04000000), /* 800x600@56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PLL_RATE(40000000, 0x00102864, 0x04000000), /* 800x600@60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PLL_RATE(49500000, 0x00103164, 0x04800000), /* 800x600@75 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PLL_RATE(50000000, 0x00103264, 0x04000000), /* 800x600@72 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PLL_RATE(56250000, 0x00103864, 0x04400000), /* 800x600@85 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PLL_RATE(65000000, 0x00104164, 0x04000000), /* 1024x768@60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PLL_RATE(74375000, 0x00104a64, 0x04600000), /* 1280x720@60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PLL_RATE(75000000, 0x00104b64, 0x04800000), /* 1024x768@70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PLL_RATE(78750000, 0x00104e64, 0x04c00000), /* 1024x768@75 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PLL_RATE(85500000, 0x00105564, 0x04800000), /* 1360x768@60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PLL_RATE(106500000, 0x00106a64, 0x04800000), /* 1440x900@60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PLL_RATE(108000000, 0x00106c64, 0x04000000), /* 1280x1024@60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PLL_RATE(110000000, 0x00106e64, 0x04000000), /* 1024x768@85 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PLL_RATE(135000000, 0x00105a44, 0x04000000), /* 1280x1024@75 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PLL_RATE(136750000, 0x00104462, 0x04600000), /* 1440x900@75 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PLL_RATE(148500000, 0x00104a62, 0x04400000), /* 1920x1080@60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PLL_RATE(157000000, 0x00104e62, 0x04800000), /* 1440x900@85 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PLL_RATE(157500000, 0x00104e62, 0x04c00000), /* 1280x1024@85 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PLL_RATE(162000000, 0x00105162, 0x04000000), /* 1600x1200@60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PLL_RATE(193250000, 0x00106062, 0x04a00000), /* 1920x1200@60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PNAME(osc) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "osc24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "osc32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PNAME(dbg_wclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "clk334m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "clk466m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "clk396m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "clk250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PNAME(a72_coreclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "osc24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "pll_mm0_1188m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) "pll_mm1_1296m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "clk1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "clk648m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "clk1600m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "pll_audio_1800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "pll_vga_1800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PNAME(cpu_periclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "osc24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "clk500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "clk594m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "clk466m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "clk294m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "clk334m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "clk250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "clk125m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PNAME(a53_coreclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "osc24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "clk1000m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "pll_mm0_1188m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "clk648m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "clk500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "clk800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "clk1600m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "pll_audio_1800m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PNAME(sec_wclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "osc24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "clk396m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "clk334m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "clk297m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "clk250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "clk198m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "clk148m5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "clk99m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PNAME(sd_nand_wclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "osc24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "clk49m5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "clk99m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "clk198m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "clk167m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "clk148m5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "clk125m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "clk216m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PNAME(emmc_wclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "osc24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "clk198m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "clk99m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "clk396m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "clk334m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "clk297m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "clk250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "clk148m5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PNAME(clk32_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "osc32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "clk32k768",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PNAME(usb_ref24m_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "osc32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "clk32k768",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PNAME(sys_noc_alck_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "osc24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "clk250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "clk198m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "clk148m5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "clk108m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "clk54m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "clk216m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "clk240m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PNAME(vde_aclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "clk334m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "clk594m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "clk500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "clk432m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "clk480m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "clk297m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "clk_vga", /*600MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "clk294m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PNAME(vce_aclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "clk334m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "clk594m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "clk500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "clk432m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) "clk396m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "clk297m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "clk_vga", /*600MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "clk294m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PNAME(hde_aclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "clk334m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "clk594m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "clk500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "clk432m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "clk396m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "clk297m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "clk_vga", /*600MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "clk294m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PNAME(gpu_aclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "clk334m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "clk648m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "clk594m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "clk500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "clk396m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "clk297m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "clk_vga", /*600MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "clk294m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PNAME(sappu_aclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "clk396m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "clk500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "clk250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "clk148m5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PNAME(sappu_wclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "clk198m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "clk396m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "clk334m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "clk297m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "clk250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "clk148m5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "clk125m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "clk99m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PNAME(vou_aclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "clk334m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "clk594m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "clk500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "clk432m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "clk396m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "clk297m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "clk_vga", /*600MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "clk294m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PNAME(vou_main_wclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "clk108m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "clk594m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "clk297m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "clk148m5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "clk74m25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "clk54m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "clk27m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "clk_vga",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PNAME(vou_aux_wclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "clk108m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "clk148m5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "clk74m25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "clk54m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "clk27m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "clk_vga",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "clk54m_mm0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "clk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PNAME(vou_ppu_wclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "clk334m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "clk432m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "clk396m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "clk297m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "clk250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) "clk125m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "clk198m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "clk99m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PNAME(vga_i2c_wclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "osc24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "clk99m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PNAME(viu_m0_aclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) "clk334m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) "clk432m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "clk396m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) "clk297m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "clk250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "clk125m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "clk198m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "osc24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PNAME(viu_m1_aclk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "clk198m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "clk250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "clk297m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "clk125m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "clk396m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "clk334m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "clk148m5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) "osc24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PNAME(viu_clk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "clk198m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "clk334m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "clk297m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "clk250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "clk396m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "clk125m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "clk99m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) "clk148m5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PNAME(viu_jpeg_clk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "clk334m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "clk480m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) "clk432m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) "clk396m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "clk297m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) "clk250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) "clk125m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "clk198m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PNAME(ts_sys_clk_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "clk192m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "clk167m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "clk125m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "clk99m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PNAME(wdt_ares_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) "osc24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) "clk32k"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static struct clk_zx_pll zx296718_pll_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ZX296718_PLL("pll_cpu", "osc24m", PLL_CPU_REG, pll_cpu_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ZX296718_PLL("pll_vga", "osc24m", PLL_VGA_REG, pll_vga_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static struct zx_clk_fixed_factor top_ffactor_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) FFACTOR(0, "clk4m", "osc24m", 1, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) FFACTOR(0, "clk2m", "osc24m", 1, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* pll cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) FFACTOR(0, "clk1600m", "pll_cpu", 1, 1, CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) FFACTOR(0, "clk800m", "pll_cpu", 1, 2, CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* pll mac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) FFACTOR(0, "clk25m", "pll_mac", 1, 40, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) FFACTOR(0, "clk125m", "pll_mac", 1, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) FFACTOR(0, "clk250m", "pll_mac", 1, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) FFACTOR(0, "clk50m", "pll_mac", 1, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) FFACTOR(0, "clk500m", "pll_mac", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) FFACTOR(0, "clk1000m", "pll_mac", 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) FFACTOR(0, "clk334m", "pll_mac", 1, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) FFACTOR(0, "clk167m", "pll_mac", 1, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* pll mm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) FFACTOR(0, "clk54m_mm0", "pll_mm0", 1, 22, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) FFACTOR(0, "clk74m25", "pll_mm0", 1, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) FFACTOR(0, "clk148m5", "pll_mm0", 1, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) FFACTOR(0, "clk297m", "pll_mm0", 1, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) FFACTOR(0, "clk594m", "pll_mm0", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) FFACTOR(0, "pll_mm0_1188m", "pll_mm0", 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) FFACTOR(0, "clk396m", "pll_mm0", 1, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) FFACTOR(0, "clk198m", "pll_mm0", 1, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) FFACTOR(0, "clk99m", "pll_mm0", 1, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) FFACTOR(0, "clk49m5", "pll_mm0", 1, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* pll mm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) FFACTOR(0, "clk324m", "pll_mm1", 1, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) FFACTOR(0, "clk648m", "pll_mm1", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) FFACTOR(0, "pll_mm1_1296m", "pll_mm1", 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) FFACTOR(0, "clk216m", "pll_mm1", 1, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) FFACTOR(0, "clk432m", "pll_mm1", 1, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) FFACTOR(0, "clk108m", "pll_mm1", 1, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) FFACTOR(0, "clk72m", "pll_mm1", 1, 18, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) FFACTOR(0, "clk27m", "pll_mm1", 1, 48, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) FFACTOR(0, "clk54m", "pll_mm1", 1, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* vga */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) FFACTOR(0, "pll_vga_1800m", "pll_vga", 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) FFACTOR(0, "clk_vga", "pll_vga", 1, 1, CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* pll ddr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) FFACTOR(0, "clk466m", "pll_ddr", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* pll audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) FFACTOR(0, "pll_audio_1800m", "pll_audio", 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) FFACTOR(0, "clk32k768", "pll_audio", 1, 27000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) FFACTOR(0, "clk16m384", "pll_audio", 1, 54, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) FFACTOR(0, "clk294m", "pll_audio", 1, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* pll hsic*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) FFACTOR(0, "clk240m", "pll_hsic", 1, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) FFACTOR(0, "clk480m", "pll_hsic", 1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) FFACTOR(0, "clk192m", "pll_hsic", 1, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) FFACTOR(0, "clk_pll_24m", "pll_hsic", 1, 40, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) FFACTOR(0, "emmc_mux_div2", "emmc_mux", 1, 2, CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const struct clk_div_table noc_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) { .val = 1, .div = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) { .val = 3, .div = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static struct zx_clk_div top_div_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) DIV_T(0, "sys_noc_hclk", "sys_noc_aclk", TOP_CLK_DIV0, 0, 2, 0, noc_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) DIV_T(0, "sys_noc_pclk", "sys_noc_aclk", TOP_CLK_DIV0, 4, 2, 0, noc_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static struct zx_clk_mux top_mux_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MUX(0, "dbg_mux", dbg_wclk_p, TOP_CLK_MUX0, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MUX(0, "a72_mux", a72_coreclk_p, TOP_CLK_MUX0, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MUX(0, "cpu_peri_mux", cpu_periclk_p, TOP_CLK_MUX0, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MUX_F(0, "a53_mux", a53_coreclk_p, TOP_CLK_MUX0, 0, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MUX(0, "sys_noc_aclk", sys_noc_alck_p, TOP_CLK_MUX1, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MUX(0, "sec_mux", sec_wclk_p, TOP_CLK_MUX2, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MUX(0, "sd1_mux", sd_nand_wclk_p, TOP_CLK_MUX2, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MUX(0, "sd0_mux", sd_nand_wclk_p, TOP_CLK_MUX2, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MUX(0, "emmc_mux", emmc_wclk_p, TOP_CLK_MUX2, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) MUX(0, "nand_mux", sd_nand_wclk_p, TOP_CLK_MUX2, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MUX(0, "usb_ref24m_mux", usb_ref24m_p, TOP_CLK_MUX9, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MUX(0, "clk32k", clk32_p, TOP_CLK_MUX9, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MUX_F(0, "wdt_mux", wdt_ares_p, TOP_CLK_MUX9, 8, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MUX(0, "timer_mux", osc, TOP_CLK_MUX9, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MUX(0, "vde_mux", vde_aclk_p, TOP_CLK_MUX4, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MUX(0, "vce_mux", vce_aclk_p, TOP_CLK_MUX4, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MUX(0, "hde_mux", hde_aclk_p, TOP_CLK_MUX4, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MUX(0, "gpu_mux", gpu_aclk_p, TOP_CLK_MUX5, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MUX(0, "sappu_a_mux", sappu_aclk_p, TOP_CLK_MUX5, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MUX(0, "sappu_w_mux", sappu_wclk_p, TOP_CLK_MUX5, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MUX(0, "vou_a_mux", vou_aclk_p, TOP_CLK_MUX7, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MUX_F(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7, 4, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MUX_F(0, "vou_aux_w_mux", vou_aux_wclk_p, TOP_CLK_MUX7, 8, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MUX(0, "vou_ppu_w_mux", vou_ppu_wclk_p, TOP_CLK_MUX7, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MUX(0, "vga_i2c_mux", vga_i2c_wclk_p, TOP_CLK_MUX7, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MUX(0, "viu_m0_a_mux", viu_m0_aclk_p, TOP_CLK_MUX6, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MUX(0, "viu_m1_a_mux", viu_m1_aclk_p, TOP_CLK_MUX6, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MUX(0, "viu_w_mux", viu_clk_p, TOP_CLK_MUX6, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) MUX(0, "viu_jpeg_w_mux", viu_jpeg_clk_p, TOP_CLK_MUX6, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) MUX(0, "ts_sys_mux", ts_sys_clk_p, TOP_CLK_MUX6, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static struct zx_clk_gate top_gate_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) GATE(CPU_DBG_GATE, "dbg_wclk", "dbg_mux", TOP_CLK_GATE0, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) GATE(A72_GATE, "a72_coreclk", "a72_mux", TOP_CLK_GATE0, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) GATE(CPU_PERI_GATE, "cpu_peri", "cpu_peri_mux", TOP_CLK_GATE0, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) GATE(A53_GATE, "a53_coreclk", "a53_mux", TOP_CLK_GATE0, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) GATE(SD1_WCLK, "sd1_wclk", "sd1_mux", TOP_CLK_GATE1, 13, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) GATE(SD0_WCLK, "sd0_wclk", "sd0_mux", TOP_CLK_GATE1, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) GATE(EMMC_WCLK, "emmc_wclk", "emmc_mux_div2", TOP_CLK_GATE0, 5, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) GATE(EMMC_NAND_AXI, "emmc_nand_aclk", "sys_noc_aclk", TOP_CLK_GATE1, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) GATE(NAND_WCLK, "nand_wclk", "nand_mux", TOP_CLK_GATE0, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) GATE(EMMC_NAND_AHB, "emmc_nand_hclk", "sys_noc_hclk", TOP_CLK_GATE1, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) GATE(0, "lsp1_pclk", "sys_noc_pclk", TOP_CLK_GATE2, 31, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) GATE(LSP1_148M5, "lsp1_148m5", "clk148m5", TOP_CLK_GATE2, 30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) GATE(LSP1_99M, "lsp1_99m", "clk99m", TOP_CLK_GATE2, 29, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) GATE(LSP1_24M, "lsp1_24m", "osc24m", TOP_CLK_GATE2, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) GATE(LSP0_74M25, "lsp0_74m25", "clk74m25", TOP_CLK_GATE2, 25, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) GATE(0, "lsp0_pclk", "sys_noc_pclk", TOP_CLK_GATE2, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) GATE(LSP0_32K, "lsp0_32k", "osc32k", TOP_CLK_GATE2, 23, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) GATE(LSP0_148M5, "lsp0_148m5", "clk148m5", TOP_CLK_GATE2, 22, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) GATE(LSP0_99M, "lsp0_99m", "clk99m", TOP_CLK_GATE2, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) GATE(LSP0_24M, "lsp0_24m", "osc24m", TOP_CLK_GATE2, 20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) GATE(AUDIO_99M, "audio_99m", "clk99m", TOP_CLK_GATE5, 27, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) GATE(AUDIO_24M, "audio_24m", "osc24m", TOP_CLK_GATE5, 28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) GATE(AUDIO_16M384, "audio_16m384", "clk16m384", TOP_CLK_GATE5, 29, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) GATE(AUDIO_32K, "audio_32k", "clk32k", TOP_CLK_GATE5, 30, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) GATE(WDT_WCLK, "wdt_wclk", "wdt_mux", TOP_CLK_GATE6, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) GATE(TIMER_WCLK, "timer_wclk", "timer_mux", TOP_CLK_GATE6, 5, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) GATE(VDE_ACLK, "vde_aclk", "vde_mux", TOP_CLK_GATE3, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) GATE(VCE_ACLK, "vce_aclk", "vce_mux", TOP_CLK_GATE3, 4, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) GATE(HDE_ACLK, "hde_aclk", "hde_mux", TOP_CLK_GATE3, 8, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) GATE(GPU_ACLK, "gpu_aclk", "gpu_mux", TOP_CLK_GATE3, 16, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) GATE(SAPPU_ACLK, "sappu_aclk", "sappu_a_mux", TOP_CLK_GATE3, 20, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) GATE(SAPPU_WCLK, "sappu_wclk", "sappu_w_mux", TOP_CLK_GATE3, 22, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) GATE(VOU_ACLK, "vou_aclk", "vou_a_mux", TOP_CLK_GATE4, 16, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GATE(VOU_MAIN_WCLK, "vou_main_wclk", "vou_main_w_mux", TOP_CLK_GATE4, 18, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) GATE(VOU_AUX_WCLK, "vou_aux_wclk", "vou_aux_w_mux", TOP_CLK_GATE4, 19, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) GATE(VOU_PPU_WCLK, "vou_ppu_wclk", "vou_ppu_w_mux", TOP_CLK_GATE4, 20, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) GATE(MIPI_CFG_CLK, "mipi_cfg_clk", "osc24m", TOP_CLK_GATE4, 21, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) GATE(VGA_I2C_WCLK, "vga_i2c_wclk", "vga_i2c_mux", TOP_CLK_GATE4, 23, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) GATE(MIPI_REF_CLK, "mipi_ref_clk", "clk27m", TOP_CLK_GATE4, 24, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) GATE(HDMI_OSC_CEC, "hdmi_osc_cec", "clk2m", TOP_CLK_GATE4, 22, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) GATE(HDMI_OSC_CLK, "hdmi_osc_clk", "clk240m", TOP_CLK_GATE4, 25, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) GATE(HDMI_XCLK, "hdmi_xclk", "osc24m", TOP_CLK_GATE4, 26, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) GATE(VIU_M0_ACLK, "viu_m0_aclk", "viu_m0_a_mux", TOP_CLK_GATE4, 0, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) GATE(VIU_M1_ACLK, "viu_m1_aclk", "viu_m1_a_mux", TOP_CLK_GATE4, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) GATE(VIU_WCLK, "viu_wclk", "viu_w_mux", TOP_CLK_GATE4, 2, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) GATE(VIU_JPEG_WCLK, "viu_jpeg_wclk", "viu_jpeg_w_mux", TOP_CLK_GATE4, 3, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) GATE(VIU_CFG_CLK, "viu_cfg_clk", "osc24m", TOP_CLK_GATE4, 6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) GATE(TS_SYS_WCLK, "ts_sys_wclk", "ts_sys_mux", TOP_CLK_GATE5, 2, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) GATE(TS_SYS_108M, "ts_sys_108m", "clk108m", TOP_CLK_GATE5, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) GATE(USB20_HCLK, "usb20_hclk", "sys_noc_hclk", TOP_CLK_GATE2, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) GATE(USB20_PHY_CLK, "usb20_phy_clk", "usb_ref24m_mux", TOP_CLK_GATE2, 13, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) GATE(USB21_HCLK, "usb21_hclk", "sys_noc_hclk", TOP_CLK_GATE2, 14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) GATE(USB21_PHY_CLK, "usb21_phy_clk", "usb_ref24m_mux", TOP_CLK_GATE2, 15, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) GATE(GMAC_RMIICLK, "gmac_rmii_clk", "clk50m", TOP_CLK_GATE2, 3, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) GATE(GMAC_PCLK, "gmac_pclk", "clk198m", TOP_CLK_GATE2, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) GATE(GMAC_ACLK, "gmac_aclk", "clk49m5", TOP_CLK_GATE2, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) GATE(GMAC_RFCLK, "gmac_refclk", "clk25m", TOP_CLK_GATE2, 4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) GATE(SD1_AHB, "sd1_hclk", "sys_noc_hclk", TOP_CLK_GATE1, 12, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) GATE(SD0_AHB, "sd0_hclk", "sys_noc_hclk", TOP_CLK_GATE1, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) GATE(TEMPSENSOR_GATE, "tempsensor_gate", "clk4m", TOP_CLK_GATE5, 31, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static struct clk_hw_onecell_data top_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .num = TOP_NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) [TOP_NR_CLKS - 1] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int __init top_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) pr_err("%s: Unable to map clk base\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) for (i = 0; i < ARRAY_SIZE(zx296718_pll_clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) zx296718_pll_clk[i].reg_base += (uintptr_t)reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) name = zx296718_pll_clk[i].hw.init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret = clk_hw_register(NULL, &zx296718_pll_clk[i].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pr_warn("top clk %s init error!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) for (i = 0; i < ARRAY_SIZE(top_ffactor_clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (top_ffactor_clk[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) top_hw_onecell_data.hws[top_ffactor_clk[i].id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) &top_ffactor_clk[i].factor.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) name = top_ffactor_clk[i].factor.hw.init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ret = clk_hw_register(NULL, &top_ffactor_clk[i].factor.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pr_warn("top clk %s init error!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) for (i = 0; i < ARRAY_SIZE(top_mux_clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (top_mux_clk[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) top_hw_onecell_data.hws[top_mux_clk[i].id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) &top_mux_clk[i].mux.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) top_mux_clk[i].mux.reg += (uintptr_t)reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) name = top_mux_clk[i].mux.hw.init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret = clk_hw_register(NULL, &top_mux_clk[i].mux.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) pr_warn("top clk %s init error!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) for (i = 0; i < ARRAY_SIZE(top_gate_clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (top_gate_clk[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) top_hw_onecell_data.hws[top_gate_clk[i].id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) &top_gate_clk[i].gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) top_gate_clk[i].gate.reg += (uintptr_t)reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) name = top_gate_clk[i].gate.hw.init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret = clk_hw_register(NULL, &top_gate_clk[i].gate.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) pr_warn("top clk %s init error!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) for (i = 0; i < ARRAY_SIZE(top_div_clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (top_div_clk[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) top_hw_onecell_data.hws[top_div_clk[i].id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) &top_div_clk[i].div.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) top_div_clk[i].div.reg += (uintptr_t)reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) name = top_div_clk[i].div.hw.init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = clk_hw_register(NULL, &top_div_clk[i].div.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) pr_warn("top clk %s init error!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) &top_hw_onecell_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) pr_err("failed to register top clk provider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static const struct clk_div_table common_even_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) { .val = 0, .div = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) { .val = 1, .div = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) { .val = 3, .div = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) { .val = 5, .div = 6, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) { .val = 7, .div = 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) { .val = 9, .div = 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) { .val = 11, .div = 12, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) { .val = 13, .div = 14, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) { .val = 15, .div = 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static const struct clk_div_table common_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) { .val = 0, .div = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) { .val = 1, .div = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) { .val = 2, .div = 3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) { .val = 3, .div = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) { .val = 4, .div = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) { .val = 5, .div = 6, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) { .val = 6, .div = 7, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) { .val = 7, .div = 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) { .val = 8, .div = 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) { .val = 9, .div = 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) { .val = 10, .div = 11, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) { .val = 11, .div = 12, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) { .val = 12, .div = 13, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) { .val = 13, .div = 14, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) { .val = 14, .div = 15, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) { .val = 15, .div = 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PNAME(lsp0_wclk_common_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) "lsp0_24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) "lsp0_99m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PNAME(lsp0_wclk_timer3_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "timer3_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) "lsp0_32k"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PNAME(lsp0_wclk_timer4_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) "timer4_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) "lsp0_32k"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PNAME(lsp0_wclk_timer5_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) "timer5_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) "lsp0_32k"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PNAME(lsp0_wclk_spifc0_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) "lsp0_148m5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) "lsp0_24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) "lsp0_99m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) "lsp0_74m25"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PNAME(lsp0_wclk_ssp_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) "lsp0_148m5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) "lsp0_99m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) "lsp0_24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static struct zx_clk_mux lsp0_mux_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) MUX(0, "timer3_wclk_mux", lsp0_wclk_timer3_p, LSP0_TIMER3_CLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) MUX(0, "timer4_wclk_mux", lsp0_wclk_timer4_p, LSP0_TIMER4_CLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) MUX(0, "timer5_wclk_mux", lsp0_wclk_timer5_p, LSP0_TIMER5_CLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) MUX(0, "uart3_wclk_mux", lsp0_wclk_common_p, LSP0_UART3_CLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) MUX(0, "uart1_wclk_mux", lsp0_wclk_common_p, LSP0_UART1_CLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) MUX(0, "uart2_wclk_mux", lsp0_wclk_common_p, LSP0_UART2_CLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) MUX(0, "spifc0_wclk_mux", lsp0_wclk_spifc0_p, LSP0_SPIFC0_CLK, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) MUX(0, "i2c4_wclk_mux", lsp0_wclk_common_p, LSP0_I2C4_CLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) MUX(0, "i2c5_wclk_mux", lsp0_wclk_common_p, LSP0_I2C5_CLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) MUX(0, "ssp0_wclk_mux", lsp0_wclk_ssp_p, LSP0_SSP0_CLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) MUX(0, "ssp1_wclk_mux", lsp0_wclk_ssp_p, LSP0_SSP1_CLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) MUX(0, "i2c3_wclk_mux", lsp0_wclk_common_p, LSP0_I2C3_CLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static struct zx_clk_gate lsp0_gate_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) GATE(LSP0_TIMER3_WCLK, "timer3_wclk", "timer3_wclk_mux", LSP0_TIMER3_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) GATE(LSP0_TIMER4_WCLK, "timer4_wclk", "timer4_wclk_mux", LSP0_TIMER4_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) GATE(LSP0_TIMER5_WCLK, "timer5_wclk", "timer5_wclk_mux", LSP0_TIMER5_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) GATE(LSP0_UART3_WCLK, "uart3_wclk", "uart3_wclk_mux", LSP0_UART3_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) GATE(LSP0_UART1_WCLK, "uart1_wclk", "uart1_wclk_mux", LSP0_UART1_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) GATE(LSP0_UART2_WCLK, "uart2_wclk", "uart2_wclk_mux", LSP0_UART2_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) GATE(LSP0_SPIFC0_WCLK, "spifc0_wclk", "spifc0_wclk_mux", LSP0_SPIFC0_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) GATE(LSP0_I2C4_WCLK, "i2c4_wclk", "i2c4_wclk_mux", LSP0_I2C4_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) GATE(LSP0_I2C5_WCLK, "i2c5_wclk", "i2c5_wclk_mux", LSP0_I2C5_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) GATE(LSP0_SSP0_WCLK, "ssp0_wclk", "ssp0_div", LSP0_SSP0_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) GATE(LSP0_SSP1_WCLK, "ssp1_wclk", "ssp1_div", LSP0_SSP1_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) GATE(LSP0_I2C3_WCLK, "i2c3_wclk", "i2c3_wclk_mux", LSP0_I2C3_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static struct zx_clk_div lsp0_div_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) DIV_T(0, "timer3_div", "lsp0_24m", LSP0_TIMER3_CLK, 12, 4, 0, common_even_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) DIV_T(0, "timer4_div", "lsp0_24m", LSP0_TIMER4_CLK, 12, 4, 0, common_even_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) DIV_T(0, "timer5_div", "lsp0_24m", LSP0_TIMER5_CLK, 12, 4, 0, common_even_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) DIV_T(0, "ssp0_div", "ssp0_wclk_mux", LSP0_SSP0_CLK, 12, 4, 0, common_even_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) DIV_T(0, "ssp1_div", "ssp1_wclk_mux", LSP0_SSP1_CLK, 12, 4, 0, common_even_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static struct clk_hw_onecell_data lsp0_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .num = LSP0_NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) [LSP0_NR_CLKS - 1] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static int __init lsp0_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) pr_err("%s: Unable to map clk base\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) for (i = 0; i < ARRAY_SIZE(lsp0_mux_clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (lsp0_mux_clk[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) lsp0_hw_onecell_data.hws[lsp0_mux_clk[i].id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) &lsp0_mux_clk[i].mux.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) lsp0_mux_clk[i].mux.reg += (uintptr_t)reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) name = lsp0_mux_clk[i].mux.hw.init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ret = clk_hw_register(NULL, &lsp0_mux_clk[i].mux.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) pr_warn("lsp0 clk %s init error!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) for (i = 0; i < ARRAY_SIZE(lsp0_gate_clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (lsp0_gate_clk[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) lsp0_hw_onecell_data.hws[lsp0_gate_clk[i].id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) &lsp0_gate_clk[i].gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) lsp0_gate_clk[i].gate.reg += (uintptr_t)reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) name = lsp0_gate_clk[i].gate.hw.init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ret = clk_hw_register(NULL, &lsp0_gate_clk[i].gate.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) pr_warn("lsp0 clk %s init error!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) for (i = 0; i < ARRAY_SIZE(lsp0_div_clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (lsp0_div_clk[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) lsp0_hw_onecell_data.hws[lsp0_div_clk[i].id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) &lsp0_div_clk[i].div.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) lsp0_div_clk[i].div.reg += (uintptr_t)reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) name = lsp0_div_clk[i].div.hw.init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = clk_hw_register(NULL, &lsp0_div_clk[i].div.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) pr_warn("lsp0 clk %s init error!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) &lsp0_hw_onecell_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) pr_err("failed to register lsp0 clk provider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) PNAME(lsp1_wclk_common_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) "lsp1_24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) "lsp1_99m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) PNAME(lsp1_wclk_ssp_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) "lsp1_148m5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) "lsp1_99m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) "lsp1_24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static struct zx_clk_mux lsp1_mux_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) MUX(0, "uart4_wclk_mux", lsp1_wclk_common_p, LSP1_UART4_CLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) MUX(0, "uart5_wclk_mux", lsp1_wclk_common_p, LSP1_UART5_CLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) MUX(0, "pwm_wclk_mux", lsp1_wclk_common_p, LSP1_PWM_CLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) MUX(0, "i2c2_wclk_mux", lsp1_wclk_common_p, LSP1_I2C2_CLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) MUX(0, "ssp2_wclk_mux", lsp1_wclk_ssp_p, LSP1_SSP2_CLK, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) MUX(0, "ssp3_wclk_mux", lsp1_wclk_ssp_p, LSP1_SSP3_CLK, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) MUX(0, "ssp4_wclk_mux", lsp1_wclk_ssp_p, LSP1_SSP4_CLK, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) MUX(0, "usim1_wclk_mux", lsp1_wclk_common_p, LSP1_USIM1_CLK, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static struct zx_clk_div lsp1_div_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) DIV_T(0, "pwm_div", "pwm_wclk_mux", LSP1_PWM_CLK, 12, 4, CLK_SET_RATE_PARENT, common_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) DIV_T(0, "ssp2_div", "ssp2_wclk_mux", LSP1_SSP2_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) DIV_T(0, "ssp3_div", "ssp3_wclk_mux", LSP1_SSP3_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) DIV_T(0, "ssp4_div", "ssp4_wclk_mux", LSP1_SSP4_CLK, 12, 4, CLK_SET_RATE_PARENT, common_even_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static struct zx_clk_gate lsp1_gate_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) GATE(LSP1_UART4_WCLK, "lsp1_uart4_wclk", "uart4_wclk_mux", LSP1_UART4_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) GATE(LSP1_UART5_WCLK, "lsp1_uart5_wclk", "uart5_wclk_mux", LSP1_UART5_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) GATE(LSP1_PWM_WCLK, "lsp1_pwm_wclk", "pwm_div", LSP1_PWM_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) GATE(LSP1_PWM_PCLK, "lsp1_pwm_pclk", "lsp1_pclk", LSP1_PWM_CLK, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) GATE(LSP1_I2C2_WCLK, "lsp1_i2c2_wclk", "i2c2_wclk_mux", LSP1_I2C2_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) GATE(LSP1_SSP2_WCLK, "lsp1_ssp2_wclk", "ssp2_div", LSP1_SSP2_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) GATE(LSP1_SSP3_WCLK, "lsp1_ssp3_wclk", "ssp3_div", LSP1_SSP3_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) GATE(LSP1_SSP4_WCLK, "lsp1_ssp4_wclk", "ssp4_div", LSP1_SSP4_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) GATE(LSP1_USIM1_WCLK, "lsp1_usim1_wclk", "usim1_wclk_mux", LSP1_USIM1_CLK, 1, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static struct clk_hw_onecell_data lsp1_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .num = LSP1_NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) [LSP1_NR_CLKS - 1] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static int __init lsp1_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) pr_err("%s: Unable to map clk base\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) for (i = 0; i < ARRAY_SIZE(lsp1_mux_clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (lsp1_mux_clk[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) lsp1_hw_onecell_data.hws[lsp1_mux_clk[i].id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) &lsp0_mux_clk[i].mux.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) lsp1_mux_clk[i].mux.reg += (uintptr_t)reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) name = lsp1_mux_clk[i].mux.hw.init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ret = clk_hw_register(NULL, &lsp1_mux_clk[i].mux.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) pr_warn("lsp1 clk %s init error!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) for (i = 0; i < ARRAY_SIZE(lsp1_gate_clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (lsp1_gate_clk[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) lsp1_hw_onecell_data.hws[lsp1_gate_clk[i].id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) &lsp1_gate_clk[i].gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) lsp1_gate_clk[i].gate.reg += (uintptr_t)reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) name = lsp1_gate_clk[i].gate.hw.init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ret = clk_hw_register(NULL, &lsp1_gate_clk[i].gate.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) pr_warn("lsp1 clk %s init error!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) for (i = 0; i < ARRAY_SIZE(lsp1_div_clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (lsp1_div_clk[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) lsp1_hw_onecell_data.hws[lsp1_div_clk[i].id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) &lsp1_div_clk[i].div.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) lsp1_div_clk[i].div.reg += (uintptr_t)reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) name = lsp1_div_clk[i].div.hw.init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ret = clk_hw_register(NULL, &lsp1_div_clk[i].div.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) pr_warn("lsp1 clk %s init error!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) &lsp1_hw_onecell_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) pr_err("failed to register lsp1 clk provider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) PNAME(audio_wclk_common_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) "audio_99m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) "audio_24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) PNAME(audio_timer_p) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) "audio_24m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) "audio_32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static struct zx_clk_mux audio_mux_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) MUX(I2S0_WCLK_MUX, "i2s0_wclk_mux", audio_wclk_common_p, AUDIO_I2S0_CLK, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) MUX(I2S1_WCLK_MUX, "i2s1_wclk_mux", audio_wclk_common_p, AUDIO_I2S1_CLK, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) MUX(I2S2_WCLK_MUX, "i2s2_wclk_mux", audio_wclk_common_p, AUDIO_I2S2_CLK, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) MUX(I2S3_WCLK_MUX, "i2s3_wclk_mux", audio_wclk_common_p, AUDIO_I2S3_CLK, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) MUX(0, "i2c0_wclk_mux", audio_wclk_common_p, AUDIO_I2C0_CLK, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) MUX(0, "spdif0_wclk_mux", audio_wclk_common_p, AUDIO_SPDIF0_CLK, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) MUX(0, "spdif1_wclk_mux", audio_wclk_common_p, AUDIO_SPDIF1_CLK, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) MUX(0, "timer_wclk_mux", audio_timer_p, AUDIO_TIMER_CLK, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static struct clk_zx_audio_divider audio_adiv_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) AUDIO_DIV(0, "i2s0_wclk_div", "i2s0_wclk_mux", AUDIO_I2S0_DIV_CFG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) AUDIO_DIV(0, "i2s1_wclk_div", "i2s1_wclk_mux", AUDIO_I2S1_DIV_CFG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) AUDIO_DIV(0, "i2s2_wclk_div", "i2s2_wclk_mux", AUDIO_I2S2_DIV_CFG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) AUDIO_DIV(0, "i2s3_wclk_div", "i2s3_wclk_mux", AUDIO_I2S3_DIV_CFG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) AUDIO_DIV(0, "spdif0_wclk_div", "spdif0_wclk_mux", AUDIO_SPDIF0_DIV_CFG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) AUDIO_DIV(0, "spdif1_wclk_div", "spdif1_wclk_mux", AUDIO_SPDIF1_DIV_CFG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static struct zx_clk_div audio_div_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) DIV_T(0, "tdm_wclk_div", "audio_16m384", AUDIO_TDM_CLK, 8, 4, 0, common_div_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static struct zx_clk_gate audio_gate_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) GATE(AUDIO_I2S0_WCLK, "i2s0_wclk", "i2s0_wclk_div", AUDIO_I2S0_CLK, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) GATE(AUDIO_I2S1_WCLK, "i2s1_wclk", "i2s1_wclk_div", AUDIO_I2S1_CLK, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) GATE(AUDIO_I2S2_WCLK, "i2s2_wclk", "i2s2_wclk_div", AUDIO_I2S2_CLK, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) GATE(AUDIO_I2S3_WCLK, "i2s3_wclk", "i2s3_wclk_div", AUDIO_I2S3_CLK, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) GATE(AUDIO_I2S0_PCLK, "i2s0_pclk", "clk49m5", AUDIO_I2S0_CLK, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) GATE(AUDIO_I2S1_PCLK, "i2s1_pclk", "clk49m5", AUDIO_I2S1_CLK, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) GATE(AUDIO_I2S2_PCLK, "i2s2_pclk", "clk49m5", AUDIO_I2S2_CLK, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) GATE(AUDIO_I2S3_PCLK, "i2s3_pclk", "clk49m5", AUDIO_I2S3_CLK, 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) GATE(AUDIO_I2C0_WCLK, "i2c0_wclk", "i2c0_wclk_mux", AUDIO_I2C0_CLK, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) GATE(AUDIO_SPDIF0_WCLK, "spdif0_wclk", "spdif0_wclk_div", AUDIO_SPDIF0_CLK, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) GATE(AUDIO_SPDIF1_WCLK, "spdif1_wclk", "spdif1_wclk_div", AUDIO_SPDIF1_CLK, 9, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) GATE(AUDIO_TDM_WCLK, "tdm_wclk", "tdm_wclk_div", AUDIO_TDM_CLK, 17, CLK_SET_RATE_PARENT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) GATE(AUDIO_TS_PCLK, "tempsensor_pclk", "clk49m5", AUDIO_TS_CLK, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static struct clk_hw_onecell_data audio_hw_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .num = AUDIO_NR_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .hws = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) [AUDIO_NR_CLKS - 1] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static int __init audio_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (!reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) pr_err("%s: Unable to map audio clk base\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) for (i = 0; i < ARRAY_SIZE(audio_mux_clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (audio_mux_clk[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) audio_hw_onecell_data.hws[audio_mux_clk[i].id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) &audio_mux_clk[i].mux.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) audio_mux_clk[i].mux.reg += (uintptr_t)reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) name = audio_mux_clk[i].mux.hw.init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ret = clk_hw_register(NULL, &audio_mux_clk[i].mux.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) pr_warn("audio clk %s init error!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) for (i = 0; i < ARRAY_SIZE(audio_adiv_clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (audio_adiv_clk[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) audio_hw_onecell_data.hws[audio_adiv_clk[i].id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) &audio_adiv_clk[i].hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) audio_adiv_clk[i].reg_base += (uintptr_t)reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) name = audio_adiv_clk[i].hw.init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ret = clk_hw_register(NULL, &audio_adiv_clk[i].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) pr_warn("audio clk %s init error!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) for (i = 0; i < ARRAY_SIZE(audio_div_clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (audio_div_clk[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) audio_hw_onecell_data.hws[audio_div_clk[i].id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) &audio_div_clk[i].div.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) audio_div_clk[i].div.reg += (uintptr_t)reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) name = audio_div_clk[i].div.hw.init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ret = clk_hw_register(NULL, &audio_div_clk[i].div.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) pr_warn("audio clk %s init error!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) for (i = 0; i < ARRAY_SIZE(audio_gate_clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (audio_gate_clk[i].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) audio_hw_onecell_data.hws[audio_gate_clk[i].id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) &audio_gate_clk[i].gate.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) audio_gate_clk[i].gate.reg += (uintptr_t)reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) name = audio_gate_clk[i].gate.hw.init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ret = clk_hw_register(NULL, &audio_gate_clk[i].gate.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) pr_warn("audio clk %s init error!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) &audio_hw_onecell_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) pr_err("failed to register audio clk provider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static const struct of_device_id zx_clkc_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) { .compatible = "zte,zx296718-topcrm", .data = &top_clocks_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) { .compatible = "zte,zx296718-lsp0crm", .data = &lsp0_clocks_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) { .compatible = "zte,zx296718-lsp1crm", .data = &lsp1_clocks_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) { .compatible = "zte,zx296718-audiocrm", .data = &audio_clocks_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static int zx_clkc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) int (*init_fn)(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) init_fn = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (!init_fn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dev_err(&pdev->dev, "Error: No device match found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return init_fn(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static struct platform_driver zx_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .probe = zx_clkc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .name = "zx296718-clkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .of_match_table = zx_clkc_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static int __init zx_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return platform_driver_register(&zx_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) core_initcall(zx_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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