Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2014 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2014 ZTE Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <dt-bindings/clock/zx296702-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) static DEFINE_SPINLOCK(reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) static void __iomem *topcrm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) static void __iomem *lsp0crpm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) static void __iomem *lsp1crpm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) static struct clk *topclk[ZX296702_TOPCLK_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static struct clk *lsp0clk[ZX296702_LSP0CLK_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static struct clk *lsp1clk[ZX296702_LSP1CLK_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static struct clk_onecell_data topclk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static struct clk_onecell_data lsp0clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static struct clk_onecell_data lsp1clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CLK_MUX			(topcrm_base + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CLK_DIV			(topcrm_base + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CLK_EN0			(topcrm_base + 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CLK_EN1			(topcrm_base + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define VOU_LOCAL_CLKEN		(topcrm_base + 0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define VOU_LOCAL_CLKSEL	(topcrm_base + 0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define VOU_LOCAL_DIV2_SET	(topcrm_base + 0x74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CLK_MUX1		(topcrm_base + 0x8c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CLK_SDMMC1		(lsp0crpm_base + 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CLK_GPIO		(lsp0crpm_base + 0x2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CLK_SPDIF0		(lsp0crpm_base + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SPDIF0_DIV		(lsp0crpm_base + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CLK_I2S0		(lsp0crpm_base + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define I2S0_DIV		(lsp0crpm_base + 0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CLK_I2S1		(lsp0crpm_base + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define I2S1_DIV		(lsp0crpm_base + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CLK_I2S2		(lsp0crpm_base + 0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define I2S2_DIV		(lsp0crpm_base + 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CLK_UART0		(lsp1crpm_base + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CLK_UART1		(lsp1crpm_base + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CLK_SDMMC0		(lsp1crpm_base + 0x2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CLK_SPDIF1		(lsp1crpm_base + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SPDIF1_DIV		(lsp1crpm_base + 0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static const struct zx_pll_config pll_a9_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	{ .rate = 700000000, .cfg0 = 0x800405d1, .cfg1 = 0x04555555 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	{ .rate = 800000000, .cfg0 = 0x80040691, .cfg1 = 0x04aaaaaa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	{ .rate = 900000000, .cfg0 = 0x80040791, .cfg1 = 0x04000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	{ .rate = 1000000000, .cfg0 = 0x80040851, .cfg1 = 0x04555555 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	{ .rate = 1100000000, .cfg0 = 0x80040911, .cfg1 = 0x04aaaaaa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{ .rate = 1200000000, .cfg0 = 0x80040a11, .cfg1 = 0x04000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static const struct clk_div_table main_hlk_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{ .val = 1, .div = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	{ .val = 3, .div = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static const struct clk_div_table a9_as1_aclk_divider[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	{ .val = 0, .div = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	{ .val = 1, .div = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	{ .val = 3, .div = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static const struct clk_div_table sec_wclk_divider[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	{ .val = 0, .div = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	{ .val = 1, .div = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	{ .val = 3, .div = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	{ .val = 5, .div = 6, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	{ .val = 7, .div = 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static const char * const matrix_aclk_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	"pll_mm0_198M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	"osc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	"clk_148M5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	"pll_lsp_104M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static const char * const a9_wclk_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	"pll_a9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	"osc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	"clk_500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	"clk_250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static const char * const a9_as1_aclk_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	"clk_250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	"osc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	"pll_mm0_396M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	"pll_mac_333M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const char * const a9_trace_clkin_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	"clk_74M25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	"pll_mm1_108M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	"clk_125",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	"clk_148M5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const char * const decppu_aclk_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	"clk_250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	"pll_mm0_198M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	"pll_lsp_104M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	"pll_audio_294M912",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const char * const vou_main_wclk_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	"clk_148M5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	"clk_74M25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	"clk_27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	"pll_mm1_54M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const char * const vou_scaler_wclk_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	"clk_250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	"pll_mac_333M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	"pll_audio_294M912",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	"pll_mm0_198M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const char * const r2d_wclk_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	"pll_audio_294M912",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	"pll_mac_333M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	"pll_a9_350M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	"pll_mm0_396M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const char * const ddr_wclk_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	"pll_mac_333M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	"pll_ddr_266M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	"pll_audio_294M912",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	"pll_mm0_198M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const char * const nand_wclk_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	"pll_lsp_104M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	"osc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const char * const lsp_26_wclk_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	"pll_lsp_26M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	"osc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const char * const vl0_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	"vou_main_channel_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	"vou_aux_channel_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const char * const hdmi_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	"vou_main_channel_wclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	"vou_aux_channel_wclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const char * const sdmmc0_wclk_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	"lsp1_104M_wclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	"lsp1_26M_wclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const char * const sdmmc1_wclk_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	"lsp0_104M_wclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	"lsp0_26M_wclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const char * const uart_wclk_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	"lsp1_104M_wclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	"lsp1_26M_wclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const char * const spdif0_wclk_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	"lsp0_104M_wclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	"lsp0_26M_wclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const char * const spdif1_wclk_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	"lsp1_104M_wclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	"lsp1_26M_wclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const char * const i2s_wclk_sel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	"lsp0_104M_wclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	"lsp0_26M_wclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static inline struct clk *zx_divtbl(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				    void __iomem *reg, u8 shift, u8 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 				    const struct clk_div_table *table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return clk_register_divider_table(NULL, name, parent, 0, reg, shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 					  width, 0, table, &reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static inline struct clk *zx_div(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 				 void __iomem *reg, u8 shift, u8 width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	return clk_register_divider(NULL, name, parent, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				    reg, shift, width, 0, &reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static inline struct clk *zx_mux(const char *name, const char * const *parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		int num_parents, void __iomem *reg, u8 shift, u8 width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return clk_register_mux(NULL, name, parents, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				0, reg, shift, width, 0, &reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static inline struct clk *zx_gate(const char *name, const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 				  void __iomem *reg, u8 shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	return clk_register_gate(NULL, name, parent, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 				 reg, shift, CLK_SET_RATE_PARENT, &reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void __init zx296702_top_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct clk **clk = topclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	topcrm_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	WARN_ON(!topcrm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	clk[ZX296702_OSC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		clk_register_fixed_rate(NULL, "osc", NULL, 0, 30000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	clk[ZX296702_PLL_A9] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		clk_register_zx_pll("pll_a9", "osc", 0, topcrm_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				+ 0x01c, pll_a9_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				ARRAY_SIZE(pll_a9_config), &reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	/* TODO: pll_a9_350M look like changeble follow a9 pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	clk[ZX296702_PLL_A9_350M] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		clk_register_fixed_rate(NULL, "pll_a9_350M", "osc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 				350000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	clk[ZX296702_PLL_MAC_1000M] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		clk_register_fixed_rate(NULL, "pll_mac_1000M", "osc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 				1000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	clk[ZX296702_PLL_MAC_333M] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		clk_register_fixed_rate(NULL, "pll_mac_333M",	 "osc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 				333000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	clk[ZX296702_PLL_MM0_1188M] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		clk_register_fixed_rate(NULL, "pll_mm0_1188M", "osc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 				1188000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	clk[ZX296702_PLL_MM0_396M] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		clk_register_fixed_rate(NULL, "pll_mm0_396M",  "osc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				396000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	clk[ZX296702_PLL_MM0_198M] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		clk_register_fixed_rate(NULL, "pll_mm0_198M",  "osc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 				198000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	clk[ZX296702_PLL_MM1_108M] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		clk_register_fixed_rate(NULL, "pll_mm1_108M",  "osc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 				108000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	clk[ZX296702_PLL_MM1_72M] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		clk_register_fixed_rate(NULL, "pll_mm1_72M",	 "osc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				72000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	clk[ZX296702_PLL_MM1_54M] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		clk_register_fixed_rate(NULL, "pll_mm1_54M",	 "osc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 				54000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	clk[ZX296702_PLL_LSP_104M] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		clk_register_fixed_rate(NULL, "pll_lsp_104M",  "osc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 				104000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	clk[ZX296702_PLL_LSP_26M] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		clk_register_fixed_rate(NULL, "pll_lsp_26M",	 "osc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 				26000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	clk[ZX296702_PLL_DDR_266M] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		clk_register_fixed_rate(NULL, "pll_ddr_266M",	 "osc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				266000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	clk[ZX296702_PLL_AUDIO_294M912] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		clk_register_fixed_rate(NULL, "pll_audio_294M912", "osc", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 				294912000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	/* bus clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	clk[ZX296702_MATRIX_ACLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		zx_mux("matrix_aclk", matrix_aclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 				ARRAY_SIZE(matrix_aclk_sel), CLK_MUX, 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	clk[ZX296702_MAIN_HCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		zx_divtbl("main_hclk", "matrix_aclk", CLK_DIV, 0, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 				main_hlk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	clk[ZX296702_MAIN_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		zx_divtbl("main_pclk", "matrix_aclk", CLK_DIV, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 				main_hlk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	/* cpu clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	clk[ZX296702_CLK_500] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		clk_register_fixed_factor(NULL, "clk_500", "pll_mac_1000M", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 				1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	clk[ZX296702_CLK_250] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		clk_register_fixed_factor(NULL, "clk_250", "pll_mac_1000M", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 				1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	clk[ZX296702_CLK_125] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		clk_register_fixed_factor(NULL, "clk_125", "clk_250", 0, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	clk[ZX296702_CLK_148M5] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		clk_register_fixed_factor(NULL, "clk_148M5", "pll_mm0_1188M", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 				1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	clk[ZX296702_CLK_74M25] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		clk_register_fixed_factor(NULL, "clk_74M25", "pll_mm0_1188M", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 				1, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	clk[ZX296702_A9_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		zx_mux("a9_wclk", a9_wclk_sel, ARRAY_SIZE(a9_wclk_sel), CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 				0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	clk[ZX296702_A9_AS1_ACLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		zx_mux("a9_as1_aclk_mux", a9_as1_aclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 				ARRAY_SIZE(a9_as1_aclk_sel), CLK_MUX, 4, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	clk[ZX296702_A9_TRACE_CLKIN_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		zx_mux("a9_trace_clkin_mux", a9_trace_clkin_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 				ARRAY_SIZE(a9_trace_clkin_sel), CLK_MUX1, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	clk[ZX296702_A9_AS1_ACLK_DIV] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		zx_divtbl("a9_as1_aclk_div", "a9_as1_aclk_mux", CLK_DIV, 4, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 				a9_as1_aclk_divider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	/* multi-media clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	clk[ZX296702_CLK_2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		clk_register_fixed_factor(NULL, "clk_2", "pll_mm1_72M", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 				1, 36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	clk[ZX296702_CLK_27] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		clk_register_fixed_factor(NULL, "clk_27", "pll_mm1_54M", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 				1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	clk[ZX296702_DECPPU_ACLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		zx_mux("decppu_aclk_mux", decppu_aclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 				ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 6, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	clk[ZX296702_PPU_ACLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		zx_mux("ppu_aclk_mux", decppu_aclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 				ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 8, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	clk[ZX296702_MALI400_ACLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		zx_mux("mali400_aclk_mux", decppu_aclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 				ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 12, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	clk[ZX296702_VOU_ACLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		zx_mux("vou_aclk_mux", decppu_aclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 				ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 10, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	clk[ZX296702_VOU_MAIN_WCLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		zx_mux("vou_main_wclk_mux", vou_main_wclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 				ARRAY_SIZE(vou_main_wclk_sel), CLK_MUX, 14, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	clk[ZX296702_VOU_AUX_WCLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		zx_mux("vou_aux_wclk_mux", vou_main_wclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 				ARRAY_SIZE(vou_main_wclk_sel), CLK_MUX, 16, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	clk[ZX296702_VOU_SCALER_WCLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		zx_mux("vou_scaler_wclk_mux", vou_scaler_wclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 				ARRAY_SIZE(vou_scaler_wclk_sel), CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 				18, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	clk[ZX296702_R2D_ACLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		zx_mux("r2d_aclk_mux", decppu_aclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 				ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 20, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	clk[ZX296702_R2D_WCLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		zx_mux("r2d_wclk_mux", r2d_wclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 				ARRAY_SIZE(r2d_wclk_sel), CLK_MUX, 22, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	/* other clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	clk[ZX296702_CLK_50] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		clk_register_fixed_factor(NULL, "clk_50", "pll_mac_1000M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 				0, 1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	clk[ZX296702_CLK_25] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		clk_register_fixed_factor(NULL, "clk_25", "pll_mac_1000M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 				0, 1, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	clk[ZX296702_CLK_12] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		clk_register_fixed_factor(NULL, "clk_12", "pll_mm1_72M",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 				0, 1, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	clk[ZX296702_CLK_16M384] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		clk_register_fixed_factor(NULL, "clk_16M384",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 				"pll_audio_294M912", 0, 1, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	clk[ZX296702_CLK_32K768] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		clk_register_fixed_factor(NULL, "clk_32K768", "clk_16M384",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 				0, 1, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	clk[ZX296702_SEC_WCLK_DIV] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		zx_divtbl("sec_wclk_div", "pll_lsp_104M", CLK_DIV, 6, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 				sec_wclk_divider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	clk[ZX296702_DDR_WCLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		zx_mux("ddr_wclk_mux", ddr_wclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 				ARRAY_SIZE(ddr_wclk_sel), CLK_MUX, 24, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	clk[ZX296702_NAND_WCLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		zx_mux("nand_wclk_mux", nand_wclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 				ARRAY_SIZE(nand_wclk_sel), CLK_MUX, 24, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	clk[ZX296702_LSP_26_WCLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		zx_mux("lsp_26_wclk_mux", lsp_26_wclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 				ARRAY_SIZE(lsp_26_wclk_sel), CLK_MUX, 27, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	/* gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	clk[ZX296702_A9_AS0_ACLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		zx_gate("a9_as0_aclk",	"matrix_aclk",		CLK_EN0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	clk[ZX296702_A9_AS1_ACLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		zx_gate("a9_as1_aclk",	"a9_as1_aclk_div",	CLK_EN0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	clk[ZX296702_A9_TRACE_CLKIN] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		zx_gate("a9_trace_clkin", "a9_trace_clkin_mux",	CLK_EN0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	clk[ZX296702_DECPPU_AXI_M_ACLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		zx_gate("decppu_axi_m_aclk", "decppu_aclk_mux", CLK_EN0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	clk[ZX296702_DECPPU_AHB_S_HCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		zx_gate("decppu_ahb_s_hclk",	"main_hclk",	CLK_EN0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	clk[ZX296702_PPU_AXI_M_ACLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		zx_gate("ppu_axi_m_aclk",	"ppu_aclk_mux",	CLK_EN0, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	clk[ZX296702_PPU_AHB_S_HCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		zx_gate("ppu_ahb_s_hclk",	"main_hclk",	CLK_EN0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	clk[ZX296702_VOU_AXI_M_ACLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		zx_gate("vou_axi_m_aclk",	"vou_aclk_mux",	CLK_EN0, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	clk[ZX296702_VOU_APB_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		zx_gate("vou_apb_pclk",	"main_pclk",		CLK_EN0, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	clk[ZX296702_VOU_MAIN_CHANNEL_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		zx_gate("vou_main_channel_wclk", "vou_main_wclk_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 				CLK_EN0, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	clk[ZX296702_VOU_AUX_CHANNEL_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		zx_gate("vou_aux_channel_wclk", "vou_aux_wclk_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 				CLK_EN0, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	clk[ZX296702_VOU_HDMI_OSCLK_CEC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		zx_gate("vou_hdmi_osclk_cec", "clk_2",		CLK_EN0, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	clk[ZX296702_VOU_SCALER_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		zx_gate("vou_scaler_wclk", "vou_scaler_wclk_mux", CLK_EN0, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	clk[ZX296702_MALI400_AXI_M_ACLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		zx_gate("mali400_axi_m_aclk", "mali400_aclk_mux", CLK_EN0, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	clk[ZX296702_MALI400_APB_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		zx_gate("mali400_apb_pclk",	"main_pclk",	CLK_EN0, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	clk[ZX296702_R2D_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		zx_gate("r2d_wclk",		"r2d_wclk_mux",	CLK_EN0, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	clk[ZX296702_R2D_AXI_M_ACLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		zx_gate("r2d_axi_m_aclk",	"r2d_aclk_mux",	CLK_EN0, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	clk[ZX296702_R2D_AHB_HCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		zx_gate("r2d_ahb_hclk",		"main_hclk",	CLK_EN0, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	clk[ZX296702_DDR3_AXI_S0_ACLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		zx_gate("ddr3_axi_s0_aclk",	"matrix_aclk",	CLK_EN0, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	clk[ZX296702_DDR3_APB_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		zx_gate("ddr3_apb_pclk",	"main_pclk",	CLK_EN0, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	clk[ZX296702_DDR3_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		zx_gate("ddr3_wclk",		"ddr_wclk_mux",	CLK_EN0, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	clk[ZX296702_USB20_0_AHB_HCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		zx_gate("usb20_0_ahb_hclk",	"main_hclk",	CLK_EN0, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	clk[ZX296702_USB20_0_EXTREFCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		zx_gate("usb20_0_extrefclk",	"clk_12",	CLK_EN0, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	clk[ZX296702_USB20_1_AHB_HCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		zx_gate("usb20_1_ahb_hclk",	"main_hclk",	CLK_EN0, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	clk[ZX296702_USB20_1_EXTREFCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		zx_gate("usb20_1_extrefclk",	"clk_12",	CLK_EN0, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	clk[ZX296702_USB20_2_AHB_HCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		zx_gate("usb20_2_ahb_hclk",	"main_hclk",	CLK_EN0, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	clk[ZX296702_USB20_2_EXTREFCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		zx_gate("usb20_2_extrefclk",	"clk_12",	CLK_EN0, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	clk[ZX296702_GMAC_AXI_M_ACLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		zx_gate("gmac_axi_m_aclk",	"matrix_aclk",	CLK_EN0, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	clk[ZX296702_GMAC_APB_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		zx_gate("gmac_apb_pclk",	"main_pclk",	CLK_EN0, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	clk[ZX296702_GMAC_125_CLKIN] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		zx_gate("gmac_125_clkin",	"clk_125",	CLK_EN0, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	clk[ZX296702_GMAC_RMII_CLKIN] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		zx_gate("gmac_rmii_clkin",	"clk_50",	CLK_EN0, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	clk[ZX296702_GMAC_25M_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		zx_gate("gmac_25M_clk",		"clk_25",	CLK_EN0, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	clk[ZX296702_NANDFLASH_AHB_HCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		zx_gate("nandflash_ahb_hclk", "main_hclk",	CLK_EN1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	clk[ZX296702_NANDFLASH_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		zx_gate("nandflash_wclk",     "nand_wclk_mux",	CLK_EN1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	clk[ZX296702_LSP0_APB_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		zx_gate("lsp0_apb_pclk",	"main_pclk",	CLK_EN1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	clk[ZX296702_LSP0_AHB_HCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		zx_gate("lsp0_ahb_hclk",	"main_hclk",	CLK_EN1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	clk[ZX296702_LSP0_26M_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		zx_gate("lsp0_26M_wclk",   "lsp_26_wclk_mux",	CLK_EN1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	clk[ZX296702_LSP0_104M_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		zx_gate("lsp0_104M_wclk",	"pll_lsp_104M",	CLK_EN1, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	clk[ZX296702_LSP0_16M384_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		zx_gate("lsp0_16M384_wclk",	"clk_16M384",	CLK_EN1, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	clk[ZX296702_LSP1_APB_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 		zx_gate("lsp1_apb_pclk",	"main_pclk",	CLK_EN1, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	/* FIXME: wclk enable bit is bit8. We hack it as reserved 31 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	 * UART does not work after parent clk is disabled/enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	clk[ZX296702_LSP1_26M_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		zx_gate("lsp1_26M_wclk",     "lsp_26_wclk_mux",	CLK_EN1, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	clk[ZX296702_LSP1_104M_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		zx_gate("lsp1_104M_wclk",    "pll_lsp_104M",	CLK_EN1, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	clk[ZX296702_LSP1_32K_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		zx_gate("lsp1_32K_clk",	"clk_32K768",		CLK_EN1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	clk[ZX296702_AON_HCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		zx_gate("aon_hclk",		"main_hclk",	CLK_EN1, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	clk[ZX296702_SYS_CTRL_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		zx_gate("sys_ctrl_pclk",	"main_pclk",	CLK_EN1, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	clk[ZX296702_DMA_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 		zx_gate("dma_pclk",		"main_pclk",	CLK_EN1, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	clk[ZX296702_DMA_ACLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		zx_gate("dma_aclk",		"matrix_aclk",	CLK_EN1, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	clk[ZX296702_SEC_HCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		zx_gate("sec_hclk",		"main_hclk",	CLK_EN1, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	clk[ZX296702_AES_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		zx_gate("aes_wclk",		"sec_wclk_div",	CLK_EN1, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	clk[ZX296702_DES_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		zx_gate("des_wclk",		"sec_wclk_div",	CLK_EN1, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	clk[ZX296702_IRAM_ACLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		zx_gate("iram_aclk",		"matrix_aclk",	CLK_EN1, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	clk[ZX296702_IROM_ACLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		zx_gate("irom_aclk",		"matrix_aclk",	CLK_EN1, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	clk[ZX296702_BOOT_CTRL_HCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 		zx_gate("boot_ctrl_hclk",	"main_hclk",	CLK_EN1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	clk[ZX296702_EFUSE_CLK_30] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		zx_gate("efuse_clk_30",	"osc",			CLK_EN1, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	/* TODO: add VOU Local clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	clk[ZX296702_VOU_MAIN_CHANNEL_DIV] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 		zx_div("vou_main_channel_div", "vou_main_channel_wclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 				VOU_LOCAL_DIV2_SET, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	clk[ZX296702_VOU_AUX_CHANNEL_DIV] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		zx_div("vou_aux_channel_div", "vou_aux_channel_wclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 				VOU_LOCAL_DIV2_SET, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	clk[ZX296702_VOU_TV_ENC_HD_DIV] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 		zx_div("vou_tv_enc_hd_div", "vou_tv_enc_hd_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 				VOU_LOCAL_DIV2_SET, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	clk[ZX296702_VOU_TV_ENC_SD_DIV] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 		zx_div("vou_tv_enc_sd_div", "vou_tv_enc_sd_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 				VOU_LOCAL_DIV2_SET, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	clk[ZX296702_VL0_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 		zx_mux("vl0_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 				VOU_LOCAL_CLKSEL, 8, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	clk[ZX296702_VL1_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 		zx_mux("vl1_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 				VOU_LOCAL_CLKSEL, 9, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	clk[ZX296702_VL2_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 		zx_mux("vl2_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 				VOU_LOCAL_CLKSEL, 10, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	clk[ZX296702_GL0_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		zx_mux("gl0_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 				VOU_LOCAL_CLKSEL, 5, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	clk[ZX296702_GL1_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		zx_mux("gl1_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 				VOU_LOCAL_CLKSEL, 6, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	clk[ZX296702_GL2_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 		zx_mux("gl2_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 				VOU_LOCAL_CLKSEL, 7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	clk[ZX296702_WB_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 		zx_mux("wb_mux",  vl0_sel, ARRAY_SIZE(vl0_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 				VOU_LOCAL_CLKSEL, 11, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	clk[ZX296702_HDMI_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 		zx_mux("hdmi_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 				VOU_LOCAL_CLKSEL, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	clk[ZX296702_VOU_TV_ENC_HD_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 		zx_mux("vou_tv_enc_hd_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 				VOU_LOCAL_CLKSEL, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	clk[ZX296702_VOU_TV_ENC_SD_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 		zx_mux("vou_tv_enc_sd_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 				VOU_LOCAL_CLKSEL, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	clk[ZX296702_VL0_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 		zx_gate("vl0_clk", "vl0_mux", VOU_LOCAL_CLKEN, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	clk[ZX296702_VL1_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 		zx_gate("vl1_clk", "vl1_mux", VOU_LOCAL_CLKEN, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	clk[ZX296702_VL2_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 		zx_gate("vl2_clk", "vl2_mux", VOU_LOCAL_CLKEN, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	clk[ZX296702_GL0_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 		zx_gate("gl0_clk", "gl0_mux", VOU_LOCAL_CLKEN, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	clk[ZX296702_GL1_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 		zx_gate("gl1_clk", "gl1_mux", VOU_LOCAL_CLKEN, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	clk[ZX296702_GL2_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 		zx_gate("gl2_clk", "gl2_mux", VOU_LOCAL_CLKEN, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	clk[ZX296702_WB_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 		zx_gate("wb_clk", "wb_mux", VOU_LOCAL_CLKEN, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	clk[ZX296702_CL_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 		zx_gate("cl_clk", "vou_main_channel_div", VOU_LOCAL_CLKEN, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	clk[ZX296702_MAIN_MIX_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 		zx_gate("main_mix_clk", "vou_main_channel_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 				VOU_LOCAL_CLKEN, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	clk[ZX296702_AUX_MIX_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 		zx_gate("aux_mix_clk", "vou_aux_channel_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 				VOU_LOCAL_CLKEN, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	clk[ZX296702_HDMI_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 		zx_gate("hdmi_clk", "hdmi_mux", VOU_LOCAL_CLKEN, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	clk[ZX296702_VOU_TV_ENC_HD_DAC_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 		zx_gate("vou_tv_enc_hd_dac_clk", "vou_tv_enc_hd_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 				VOU_LOCAL_CLKEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	clk[ZX296702_VOU_TV_ENC_SD_DAC_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 		zx_gate("vou_tv_enc_sd_dac_clk", "vou_tv_enc_sd_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 				VOU_LOCAL_CLKEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	/* CA9 PERIPHCLK = a9_wclk / 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	clk[ZX296702_A9_PERIPHCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 		clk_register_fixed_factor(NULL, "a9_periphclk", "a9_wclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 				0, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	for (i = 0; i < ARRAY_SIZE(topclk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 		if (IS_ERR(clk[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 			pr_err("zx296702 clk %d: register failed with %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 				i, PTR_ERR(clk[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	topclk_data.clks = topclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	topclk_data.clk_num = ARRAY_SIZE(topclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	of_clk_add_provider(np, of_clk_src_onecell_get, &topclk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) CLK_OF_DECLARE(zx296702_top_clk, "zte,zx296702-topcrm-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 		zx296702_top_clocks_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static void __init zx296702_lsp0_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	struct clk **clk = lsp0clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	lsp0crpm_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	WARN_ON(!lsp0crpm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 	/* SDMMC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 	clk[ZX296702_SDMMC1_WCLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 		zx_mux("sdmmc1_wclk_mux", sdmmc1_wclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 				ARRAY_SIZE(sdmmc1_wclk_sel), CLK_SDMMC1, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 	clk[ZX296702_SDMMC1_WCLK_DIV] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 		zx_div("sdmmc1_wclk_div", "sdmmc1_wclk_mux", CLK_SDMMC1, 12, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	clk[ZX296702_SDMMC1_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 		zx_gate("sdmmc1_wclk", "sdmmc1_wclk_div", CLK_SDMMC1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	clk[ZX296702_SDMMC1_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 		zx_gate("sdmmc1_pclk", "lsp0_apb_pclk", CLK_SDMMC1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	clk[ZX296702_GPIO_CLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 		zx_gate("gpio_clk", "lsp0_apb_pclk", CLK_GPIO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	/* SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	clk[ZX296702_SPDIF0_WCLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 		zx_mux("spdif0_wclk_mux", spdif0_wclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 				ARRAY_SIZE(spdif0_wclk_sel), CLK_SPDIF0, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	clk[ZX296702_SPDIF0_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 		zx_gate("spdif0_wclk", "spdif0_wclk_mux", CLK_SPDIF0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	clk[ZX296702_SPDIF0_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 		zx_gate("spdif0_pclk", "lsp0_apb_pclk", CLK_SPDIF0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 	clk[ZX296702_SPDIF0_DIV] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 		clk_register_zx_audio("spdif0_div", "spdif0_wclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 				SPDIF0_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 	/* I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 	clk[ZX296702_I2S0_WCLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 		zx_mux("i2s0_wclk_mux", i2s_wclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 				ARRAY_SIZE(i2s_wclk_sel), CLK_I2S0, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 	clk[ZX296702_I2S0_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 		zx_gate("i2s0_wclk", "i2s0_wclk_mux", CLK_I2S0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 	clk[ZX296702_I2S0_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 		zx_gate("i2s0_pclk", "lsp0_apb_pclk", CLK_I2S0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 	clk[ZX296702_I2S0_DIV] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 		clk_register_zx_audio("i2s0_div", "i2s0_wclk", 0, I2S0_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 	clk[ZX296702_I2S1_WCLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 		zx_mux("i2s1_wclk_mux", i2s_wclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 				ARRAY_SIZE(i2s_wclk_sel), CLK_I2S1, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 	clk[ZX296702_I2S1_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 		zx_gate("i2s1_wclk", "i2s1_wclk_mux", CLK_I2S1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 	clk[ZX296702_I2S1_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 		zx_gate("i2s1_pclk", "lsp0_apb_pclk", CLK_I2S1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 	clk[ZX296702_I2S1_DIV] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 		clk_register_zx_audio("i2s1_div", "i2s1_wclk", 0, I2S1_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 	clk[ZX296702_I2S2_WCLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 		zx_mux("i2s2_wclk_mux", i2s_wclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 				ARRAY_SIZE(i2s_wclk_sel), CLK_I2S2, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 	clk[ZX296702_I2S2_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 		zx_gate("i2s2_wclk", "i2s2_wclk_mux", CLK_I2S2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 	clk[ZX296702_I2S2_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 		zx_gate("i2s2_pclk", "lsp0_apb_pclk", CLK_I2S2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 	clk[ZX296702_I2S2_DIV] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 		clk_register_zx_audio("i2s2_div", "i2s2_wclk", 0, I2S2_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 	for (i = 0; i < ARRAY_SIZE(lsp0clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 		if (IS_ERR(clk[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 			pr_err("zx296702 clk %d: register failed with %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 				i, PTR_ERR(clk[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 	lsp0clk_data.clks = lsp0clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 	lsp0clk_data.clk_num = ARRAY_SIZE(lsp0clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 	of_clk_add_provider(np, of_clk_src_onecell_get, &lsp0clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) CLK_OF_DECLARE(zx296702_lsp0_clk, "zte,zx296702-lsp0crpm-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 		zx296702_lsp0_clocks_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static void __init zx296702_lsp1_clocks_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 	struct clk **clk = lsp1clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 	lsp1crpm_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 	WARN_ON(!lsp1crpm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 	/* UART0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 	clk[ZX296702_UART0_WCLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 		zx_mux("uart0_wclk_mux", uart_wclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 				ARRAY_SIZE(uart_wclk_sel), CLK_UART0, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 	/* FIXME: uart wclk enable bit is bit1 in. We hack it as reserved 31 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 	 * UART does not work after parent clk is disabled/enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 	clk[ZX296702_UART0_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 		zx_gate("uart0_wclk", "uart0_wclk_mux", CLK_UART0, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 	clk[ZX296702_UART0_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 		zx_gate("uart0_pclk", "lsp1_apb_pclk", CLK_UART0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 	/* UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 	clk[ZX296702_UART1_WCLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 		zx_mux("uart1_wclk_mux", uart_wclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 				ARRAY_SIZE(uart_wclk_sel), CLK_UART1, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 	clk[ZX296702_UART1_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 		zx_gate("uart1_wclk", "uart1_wclk_mux", CLK_UART1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 	clk[ZX296702_UART1_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 		zx_gate("uart1_pclk", "lsp1_apb_pclk", CLK_UART1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 	/* SDMMC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 	clk[ZX296702_SDMMC0_WCLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 		zx_mux("sdmmc0_wclk_mux", sdmmc0_wclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 				ARRAY_SIZE(sdmmc0_wclk_sel), CLK_SDMMC0, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 	clk[ZX296702_SDMMC0_WCLK_DIV] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 		zx_div("sdmmc0_wclk_div", "sdmmc0_wclk_mux", CLK_SDMMC0, 12, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 	clk[ZX296702_SDMMC0_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 		zx_gate("sdmmc0_wclk", "sdmmc0_wclk_div", CLK_SDMMC0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 	clk[ZX296702_SDMMC0_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 		zx_gate("sdmmc0_pclk", "lsp1_apb_pclk", CLK_SDMMC0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 	clk[ZX296702_SPDIF1_WCLK_MUX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 		zx_mux("spdif1_wclk_mux", spdif1_wclk_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 				ARRAY_SIZE(spdif1_wclk_sel), CLK_SPDIF1, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 	clk[ZX296702_SPDIF1_WCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 		zx_gate("spdif1_wclk", "spdif1_wclk_mux", CLK_SPDIF1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 	clk[ZX296702_SPDIF1_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 		zx_gate("spdif1_pclk", "lsp1_apb_pclk", CLK_SPDIF1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 	clk[ZX296702_SPDIF1_DIV] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 		clk_register_zx_audio("spdif1_div", "spdif1_wclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 				SPDIF1_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 	for (i = 0; i < ARRAY_SIZE(lsp1clk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 		if (IS_ERR(clk[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 			pr_err("zx296702 clk %d: register failed with %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 				i, PTR_ERR(clk[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 	lsp1clk_data.clks = lsp1clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 	lsp1clk_data.clk_num = ARRAY_SIZE(lsp1clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 	of_clk_add_provider(np, of_clk_src_onecell_get, &lsp1clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) CLK_OF_DECLARE(zx296702_lsp1_clk, "zte,zx296702-lsp1crpm-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 		zx296702_lsp1_clocks_init);