^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Atom platform clocks driver for BayTrail and CherryTrail SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Irina Tirdea <irina.tirdea@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_data/x86/clk-pmc-atom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PLT_CLK_NAME_BASE "pmc_plt_clk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PMC_CLK_CTL_OFFSET 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PMC_CLK_CTL_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PMC_CLK_NUM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PMC_CLK_CTL_GATED_ON_D3 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PMC_CLK_CTL_FORCE_ON 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PMC_CLK_CTL_FORCE_OFF 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PMC_CLK_CTL_RESERVED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PMC_MASK_CLK_CTL GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PMC_MASK_CLK_FREQ BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PMC_CLK_FREQ_XTAL (0 << 2) /* 25 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PMC_CLK_FREQ_PLL (1 << 2) /* 19.2 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct clk_plt_fixed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct clk_hw *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct clk_lookup *lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct clk_plt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct clk_lookup *lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* protect access to PMC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define to_clk_plt(_hw) container_of(_hw, struct clk_plt, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clk_plt_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct clk_plt_fixed **parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 nparents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clk_plt *clks[PMC_CLK_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct clk_lookup *mclk_lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct clk_lookup *ether_clk_lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Return an index in parent table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static inline int plt_reg_to_parent(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) switch (reg & PMC_MASK_CLK_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) case PMC_CLK_FREQ_XTAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) case PMC_CLK_FREQ_PLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Return clk index of parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static inline int plt_parent_to_reg(int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return PMC_CLK_FREQ_XTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return PMC_CLK_FREQ_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Abstract status in simpler enabled/disabled value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline int plt_reg_to_enabled(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) switch (reg & PMC_MASK_CLK_CTL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case PMC_CLK_CTL_GATED_ON_D3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case PMC_CLK_CTL_FORCE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 1; /* enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) case PMC_CLK_CTL_FORCE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case PMC_CLK_CTL_RESERVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 0; /* disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void plt_clk_reg_update(struct clk_plt *clk, u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) spin_lock_irqsave(&clk->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) tmp = readl(clk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) tmp = (tmp & ~mask) | (val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel(tmp, clk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) spin_unlock_irqrestore(&clk->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int plt_clk_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct clk_plt *clk = to_clk_plt(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) plt_clk_reg_update(clk, PMC_MASK_CLK_FREQ, plt_parent_to_reg(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static u8 plt_clk_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct clk_plt *clk = to_clk_plt(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) value = readl(clk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return plt_reg_to_parent(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int plt_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct clk_plt *clk = to_clk_plt(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) plt_clk_reg_update(clk, PMC_MASK_CLK_CTL, PMC_CLK_CTL_FORCE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void plt_clk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct clk_plt *clk = to_clk_plt(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) plt_clk_reg_update(clk, PMC_MASK_CLK_CTL, PMC_CLK_CTL_FORCE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int plt_clk_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk_plt *clk = to_clk_plt(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) value = readl(clk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return plt_reg_to_enabled(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct clk_ops plt_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .enable = plt_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .disable = plt_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .is_enabled = plt_clk_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .get_parent = plt_clk_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .set_parent = plt_clk_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .determine_rate = __clk_mux_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static struct clk_plt *plt_clk_register(struct platform_device *pdev, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) const struct pmc_clk_data *pmc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) const char **parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int num_parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct clk_plt *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (!pclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) init.name = kasprintf(GFP_KERNEL, "%s_%d", PLT_CLK_NAME_BASE, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) init.ops = &plt_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) pclk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) pclk->reg = pmc_data->base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) spin_lock_init(&pclk->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * On some systems, the pmc_plt_clocks already enabled by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * firmware are being marked as critical to avoid them being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * gated by the clock framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (pmc_data->critical && plt_clk_is_enabled(&pclk->hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) init.flags |= CLK_IS_CRITICAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret = devm_clk_hw_register(&pdev->dev, &pclk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pclk = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) goto err_free_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pclk->lookup = clkdev_hw_create(&pclk->hw, init.name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!pclk->lookup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pclk = ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) goto err_free_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) err_free_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) kfree(init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void plt_clk_unregister(struct clk_plt *pclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clkdev_drop(pclk->lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static struct clk_plt_fixed *plt_clk_register_fixed_rate(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned long fixed_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct clk_plt_fixed *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!pclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pclk->clk = clk_hw_register_fixed_rate(&pdev->dev, name, parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 0, fixed_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (IS_ERR(pclk->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ERR_CAST(pclk->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pclk->lookup = clkdev_hw_create(pclk->clk, name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (!pclk->lookup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) clk_hw_unregister_fixed_rate(pclk->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void plt_clk_unregister_fixed_rate(struct clk_plt_fixed *pclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) clkdev_drop(pclk->lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) clk_hw_unregister_fixed_rate(pclk->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void plt_clk_unregister_fixed_rate_loop(struct clk_plt_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) plt_clk_unregister_fixed_rate(data->parents[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void plt_clk_free_parent_names_loop(const char **parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) kfree_const(parent_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) kfree(parent_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void plt_clk_unregister_loop(struct clk_plt_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) plt_clk_unregister(data->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const char **plt_clk_register_parents(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct clk_plt_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) const struct pmc_clk *clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) const char **parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int nparents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) data->nparents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) while (clks[nparents].name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) nparents++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) data->parents = devm_kcalloc(&pdev->dev, nparents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) sizeof(*data->parents), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!data->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) parent_names = kcalloc(nparents, sizeof(*parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!parent_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) for (i = 0; i < nparents; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) data->parents[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) plt_clk_register_fixed_rate(pdev, clks[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) clks[i].parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) clks[i].freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (IS_ERR(data->parents[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) err = PTR_ERR(data->parents[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) goto err_unreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) parent_names[i] = kstrdup_const(clks[i].name, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) data->nparents = nparents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) err_unreg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) plt_clk_unregister_fixed_rate_loop(data, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) plt_clk_free_parent_names_loop(parent_names, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static void plt_clk_unregister_parents(struct clk_plt_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) plt_clk_unregister_fixed_rate_loop(data, data->nparents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int plt_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) const struct pmc_clk_data *pmc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) const char **parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct clk_plt_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) pmc_data = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!pmc_data || !pmc_data->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) parent_names = plt_clk_register_parents(pdev, data, pmc_data->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (IS_ERR(parent_names))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return PTR_ERR(parent_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) for (i = 0; i < PMC_CLK_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) data->clks[i] = plt_clk_register(pdev, i, pmc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) parent_names, data->nparents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (IS_ERR(data->clks[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) err = PTR_ERR(data->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) goto err_unreg_clk_plt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) data->mclk_lookup = clkdev_hw_create(&data->clks[3]->hw, "mclk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (!data->mclk_lookup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) goto err_unreg_clk_plt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) data->ether_clk_lookup = clkdev_hw_create(&data->clks[4]->hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "ether_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (!data->ether_clk_lookup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) goto err_drop_mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) plt_clk_free_parent_names_loop(parent_names, data->nparents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) platform_set_drvdata(pdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) err_drop_mclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) clkdev_drop(data->mclk_lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) err_unreg_clk_plt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) plt_clk_unregister_loop(data, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) plt_clk_unregister_parents(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) plt_clk_free_parent_names_loop(parent_names, data->nparents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int plt_clk_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct clk_plt_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) data = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) clkdev_drop(data->ether_clk_lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) clkdev_drop(data->mclk_lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) plt_clk_unregister_loop(data, PMC_CLK_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) plt_clk_unregister_parents(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static struct platform_driver plt_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .name = "clk-pmc-atom",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .probe = plt_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .remove = plt_clk_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) builtin_platform_driver(plt_clk_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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