^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2020 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Zhu YiXin <yixin.zhu@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Rahul Tanwar <rahul.tanwar@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <dt-bindings/clock/intel,lgm-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-cgu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PLL_DIV_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PLL_DDIV_WIDTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Gate0 clock shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define G_C55_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define G_QSPI_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define G_EIP197_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define G_VAULT130_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define G_TOE_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define G_SDXC_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define G_EMMC_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define G_SPIDBG_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define G_DMA3_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Gate1 clock shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define G_DMA0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define G_LEDC0_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define G_LEDC1_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define G_I2S0_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define G_I2S1_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define G_EBU_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define G_PWM_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define G_I2C0_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define G_I2C1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define G_I2C2_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define G_I2C3_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define G_SSC0_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define G_SSC1_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define G_SSC2_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define G_SSC3_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define G_GPTC0_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define G_GPTC1_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define G_GPTC2_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define G_GPTC3_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define G_ASC0_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define G_ASC1_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define G_ASC2_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define G_ASC3_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define G_PCM0_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define G_PCM1_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define G_PCM2_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Gate2 clock shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define G_PCIE10_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define G_PCIE11_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define G_PCIE30_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define G_PCIE31_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define G_PCIE20_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define G_PCIE21_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define G_PCIE40_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define G_PCIE41_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define G_XPCS0_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define G_XPCS1_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define G_XPCS2_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define G_XPCS3_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define G_SATA0_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define G_SATA1_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define G_SATA2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define G_SATA3_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Gate3 clock shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define G_ARCEM4_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define G_IDMAR1_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define G_IDMAT0_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define G_IDMAT1_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define G_IDMAT2_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define G_PPV4_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define G_GSWIPO_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define G_CQEM_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define G_XPCS5_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define G_USB1_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define G_USB2_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CGU_PLL0CZ_CFG0 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CGU_PLL0CM0_CFG0 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CGU_PLL0CM1_CFG0 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CGU_PLL0B_CFG0 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CGU_PLL1_CFG0 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CGU_PLL2_CFG0 0x0A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CGU_PLLPP_CFG0 0x0C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CGU_LJPLL3_CFG0 0x0E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CGU_LJPLL4_CFG0 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CGU_C55_PCMCR 0x18C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CGU_PCMCR 0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CGU_IF_CLK1 0x1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CGU_IF_CLK2 0x1A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CGU_GATE0 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CGU_GATE1 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CGU_GATE2 0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CGU_GATE3 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PLL_DIV(x) ((x) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PLL_SSC(x) ((x) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_NR_CLKS (LGM_GCLK_USB2 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Below table defines the pair's of regval & effective dividers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * It's more efficient to provide an explicit table due to non-linear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * relation between values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct clk_div_table pll_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { .val = 0, .div = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { .val = 1, .div = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { .val = 2, .div = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { .val = 3, .div = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { .val = 4, .div = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { .val = 5, .div = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { .val = 6, .div = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { .val = 7, .div = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { .val = 8, .div = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { .val = 9, .div = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { .val = 10, .div = 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { .val = 11, .div = 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { .val = 12, .div = 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { .val = 13, .div = 40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { .val = 14, .div = 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { .val = 15, .div = 64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct clk_div_table dcl_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { .val = 0, .div = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { .val = 1, .div = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { .val = 2, .div = 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { .val = 3, .div = 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { .val = 4, .div = 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { .val = 5, .div = 96 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct clk_parent_data pll_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { .fw_name = "osc", .name = "osc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const struct clk_parent_data pllcm_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { .fw_name = "cpu_cm", .name = "cpu_cm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct clk_parent_data emmc_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { .fw_name = "emmc4", .name = "emmc4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { .fw_name = "noc4", .name = "noc4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const struct clk_parent_data sdxc_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { .fw_name = "sdxc3", .name = "sdxc3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { .fw_name = "sdxc2", .name = "sdxc2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct clk_parent_data pcm_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { .fw_name = "v_docsis", .name = "v_docsis" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { .fw_name = "dcl", .name = "dcl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct clk_parent_data cbphy_p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { .fw_name = "dd_serdes", .name = "dd_serdes" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { .fw_name = "dd_pcie", .name = "dd_pcie" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct lgm_pll_clk_data lgm_pll_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) LGM_PLL(LGM_CLK_PLL0CZ, "pll0cz", pll_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) CGU_PLL0CZ_CFG0, TYPE_ROPLL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) LGM_PLL(LGM_CLK_PLL0CM0, "pll0cm0", pllcm_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) CGU_PLL0CM0_CFG0, TYPE_ROPLL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) LGM_PLL(LGM_CLK_PLL0CM1, "pll0cm1", pllcm_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) CGU_PLL0CM1_CFG0, TYPE_ROPLL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) LGM_PLL(LGM_CLK_PLL0B, "pll0b", pll_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) CGU_PLL0B_CFG0, TYPE_ROPLL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) LGM_PLL(LGM_CLK_PLL1, "pll1", pll_p, 0, CGU_PLL1_CFG0, TYPE_ROPLL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) LGM_PLL(LGM_CLK_PLL2, "pll2", pll_p, CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) CGU_PLL2_CFG0, TYPE_ROPLL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) LGM_PLL(LGM_CLK_PLLPP, "pllpp", pll_p, 0, CGU_PLLPP_CFG0, TYPE_ROPLL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) LGM_PLL(LGM_CLK_LJPLL3, "ljpll3", pll_p, 0, CGU_LJPLL3_CFG0, TYPE_LJPLL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) LGM_PLL(LGM_CLK_LJPLL4, "ljpll4", pll_p, 0, CGU_LJPLL4_CFG0, TYPE_LJPLL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct lgm_clk_branch lgm_branch_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) LGM_DIV(LGM_CLK_PP_HW, "pp_hw", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) LGM_DIV(LGM_CLK_PP_UC, "pp_uc", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 4, PLL_DIV_WIDTH, 25, 1, 0, 0, pll_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) LGM_DIV(LGM_CLK_PP_FXD, "pp_fxd", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) LGM_DIV(LGM_CLK_PP_TBM, "pp_tbm", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) LGM_DIV(LGM_CLK_DDR, "ddr", "pll2", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PLL_DIV(CGU_PLL2_CFG0), 0, PLL_DIV_WIDTH, 24, 1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pll_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) LGM_DIV(LGM_CLK_CM, "cpu_cm", "pll0cz", 0, PLL_DIV(CGU_PLL0CZ_CFG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) LGM_DIV(LGM_CLK_IC, "cpu_ic", "pll0cz", CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PLL_DIV(CGU_PLL0CZ_CFG0), 4, PLL_DIV_WIDTH, 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 1, 0, 0, pll_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) LGM_DIV(LGM_CLK_SDXC3, "sdxc3", "pll0cz", 0, PLL_DIV(CGU_PLL0CZ_CFG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) LGM_DIV(LGM_CLK_CPU0, "cm0", "pll0cm0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) CLK_IGNORE_UNUSED, PLL_DIV(CGU_PLL0CM0_CFG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) LGM_DIV(LGM_CLK_CPU1, "cm1", "pll0cm1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) CLK_IGNORE_UNUSED, PLL_DIV(CGU_PLL0CM1_CFG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Marking ngi_clk (next generation interconnect) and noc_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * (network on chip peripheral clk) as critical clocks because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * these are shared parent clock sources for many different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * peripherals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) LGM_DIV(LGM_CLK_NGI, "ngi", "pll0b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) (CLK_IGNORE_UNUSED|CLK_IS_CRITICAL), PLL_DIV(CGU_PLL0B_CFG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) LGM_DIV(LGM_CLK_NOC4, "noc4", "pll0b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) (CLK_IGNORE_UNUSED|CLK_IS_CRITICAL), PLL_DIV(CGU_PLL0B_CFG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 4, PLL_DIV_WIDTH, 25, 1, 0, 0, pll_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) LGM_DIV(LGM_CLK_SW, "switch", "pll0b", 0, PLL_DIV(CGU_PLL0B_CFG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) LGM_DIV(LGM_CLK_QSPI, "qspi", "pll0b", 0, PLL_DIV(CGU_PLL0B_CFG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) LGM_DIV(LGM_CLK_CT, "v_ct", "pll1", 0, PLL_DIV(CGU_PLL1_CFG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) LGM_DIV(LGM_CLK_DSP, "v_dsp", "pll1", 0, PLL_DIV(CGU_PLL1_CFG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) LGM_DIV(LGM_CLK_VIF, "v_ifclk", "pll1", 0, PLL_DIV(CGU_PLL1_CFG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) LGM_FIXED_FACTOR(LGM_CLK_EMMC4, "emmc4", "sdxc3", 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 0, 0, 0, 0, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) LGM_FIXED_FACTOR(LGM_CLK_SDXC2, "sdxc2", "noc4", 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 0, 0, 0, 0, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) LGM_MUX(LGM_CLK_EMMC, "emmc", emmc_p, 0, CGU_IF_CLK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 0, 1, CLK_MUX_ROUND_CLOSEST, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) LGM_MUX(LGM_CLK_SDXC, "sdxc", sdxc_p, 0, CGU_IF_CLK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 1, 1, CLK_MUX_ROUND_CLOSEST, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) LGM_FIXED(LGM_CLK_OSC, "osc", NULL, 0, 0, 0, 0, 0, 40000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) LGM_FIXED(LGM_CLK_SLIC, "slic", NULL, 0, CGU_IF_CLK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 8, 2, CLOCK_FLAG_VAL_INIT, 8192000, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) LGM_FIXED(LGM_CLK_DOCSIS, "v_docsis", NULL, 0, 0, 0, 0, 0, 16000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", 0, CGU_PCMCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 25, 3, 0, 0, 0, 0, dcl_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) LGM_MUX(LGM_CLK_PCM, "pcm", pcm_p, 0, CGU_C55_PCMCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 0, 1, CLK_MUX_ROUND_CLOSEST, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) LGM_FIXED_FACTOR(LGM_CLK_DDR_PHY, "ddr_phy", "ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) CLK_IGNORE_UNUSED, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 0, 0, 0, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) LGM_FIXED_FACTOR(LGM_CLK_PONDEF, "pondef", "dd_pool",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) CLK_SET_RATE_PARENT, 0, 0, 0, 0, 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) LGM_MUX(LGM_CLK_CBPHY0, "cbphy0", cbphy_p, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 0, 0, MUX_CLK_SW | CLK_MUX_ROUND_CLOSEST, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) LGM_MUX(LGM_CLK_CBPHY1, "cbphy1", cbphy_p, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 0, 0, MUX_CLK_SW | CLK_MUX_ROUND_CLOSEST, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) LGM_MUX(LGM_CLK_CBPHY2, "cbphy2", cbphy_p, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 0, 0, MUX_CLK_SW | CLK_MUX_ROUND_CLOSEST, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) LGM_MUX(LGM_CLK_CBPHY3, "cbphy3", cbphy_p, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 0, 0, MUX_CLK_SW | CLK_MUX_ROUND_CLOSEST, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) LGM_GATE(LGM_GCLK_C55, "g_c55", NULL, 0, CGU_GATE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) G_C55_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) LGM_GATE(LGM_GCLK_QSPI, "g_qspi", "qspi", 0, CGU_GATE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) G_QSPI_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) LGM_GATE(LGM_GCLK_EIP197, "g_eip197", NULL, 0, CGU_GATE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) G_EIP197_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) LGM_GATE(LGM_GCLK_VAULT, "g_vault130", NULL, 0, CGU_GATE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) G_VAULT130_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) LGM_GATE(LGM_GCLK_TOE, "g_toe", NULL, 0, CGU_GATE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) G_TOE_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) LGM_GATE(LGM_GCLK_SDXC, "g_sdxc", "sdxc", 0, CGU_GATE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) G_SDXC_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) LGM_GATE(LGM_GCLK_EMMC, "g_emmc", "emmc", 0, CGU_GATE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) G_EMMC_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) LGM_GATE(LGM_GCLK_SPI_DBG, "g_spidbg", NULL, 0, CGU_GATE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) G_SPIDBG_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) LGM_GATE(LGM_GCLK_DMA3, "g_dma3", NULL, 0, CGU_GATE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) G_DMA3_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) LGM_GATE(LGM_GCLK_DMA0, "g_dma0", NULL, 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) G_DMA0_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) LGM_GATE(LGM_GCLK_LEDC0, "g_ledc0", NULL, 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) G_LEDC0_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) LGM_GATE(LGM_GCLK_LEDC1, "g_ledc1", NULL, 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) G_LEDC1_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) LGM_GATE(LGM_GCLK_I2S0, "g_i2s0", NULL, 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) G_I2S0_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) LGM_GATE(LGM_GCLK_I2S1, "g_i2s1", NULL, 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) G_I2S1_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) LGM_GATE(LGM_GCLK_EBU, "g_ebu", NULL, 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) G_EBU_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) LGM_GATE(LGM_GCLK_PWM, "g_pwm", NULL, 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) G_PWM_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) LGM_GATE(LGM_GCLK_I2C0, "g_i2c0", NULL, 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) G_I2C0_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) LGM_GATE(LGM_GCLK_I2C1, "g_i2c1", NULL, 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) G_I2C1_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) LGM_GATE(LGM_GCLK_I2C2, "g_i2c2", NULL, 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) G_I2C2_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) LGM_GATE(LGM_GCLK_I2C3, "g_i2c3", NULL, 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) G_I2C3_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) LGM_GATE(LGM_GCLK_SSC0, "g_ssc0", "noc4", 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) G_SSC0_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) LGM_GATE(LGM_GCLK_SSC1, "g_ssc1", "noc4", 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) G_SSC1_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) LGM_GATE(LGM_GCLK_SSC2, "g_ssc2", "noc4", 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) G_SSC2_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) LGM_GATE(LGM_GCLK_SSC3, "g_ssc3", "noc4", 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) G_SSC3_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) LGM_GATE(LGM_GCLK_GPTC0, "g_gptc0", "noc4", 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) G_GPTC0_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) LGM_GATE(LGM_GCLK_GPTC1, "g_gptc1", "noc4", 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) G_GPTC1_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) LGM_GATE(LGM_GCLK_GPTC2, "g_gptc2", "noc4", 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) G_GPTC2_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) LGM_GATE(LGM_GCLK_GPTC3, "g_gptc3", "osc", 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) G_GPTC3_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) LGM_GATE(LGM_GCLK_ASC0, "g_asc0", "noc4", 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) G_ASC0_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) LGM_GATE(LGM_GCLK_ASC1, "g_asc1", "noc4", 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) G_ASC1_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) LGM_GATE(LGM_GCLK_ASC2, "g_asc2", "noc4", 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) G_ASC2_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) LGM_GATE(LGM_GCLK_ASC3, "g_asc3", "osc", 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) G_ASC3_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) LGM_GATE(LGM_GCLK_PCM0, "g_pcm0", NULL, 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) G_PCM0_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) LGM_GATE(LGM_GCLK_PCM1, "g_pcm1", NULL, 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) G_PCM1_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) LGM_GATE(LGM_GCLK_PCM2, "g_pcm2", NULL, 0, CGU_GATE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) G_PCM2_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) LGM_GATE(LGM_GCLK_PCIE10, "g_pcie10", NULL, 0, CGU_GATE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) G_PCIE10_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) LGM_GATE(LGM_GCLK_PCIE11, "g_pcie11", NULL, 0, CGU_GATE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) G_PCIE11_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) LGM_GATE(LGM_GCLK_PCIE30, "g_pcie30", NULL, 0, CGU_GATE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) G_PCIE30_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) LGM_GATE(LGM_GCLK_PCIE31, "g_pcie31", NULL, 0, CGU_GATE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) G_PCIE31_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) LGM_GATE(LGM_GCLK_PCIE20, "g_pcie20", NULL, 0, CGU_GATE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) G_PCIE20_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) LGM_GATE(LGM_GCLK_PCIE21, "g_pcie21", NULL, 0, CGU_GATE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) G_PCIE21_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) LGM_GATE(LGM_GCLK_PCIE40, "g_pcie40", NULL, 0, CGU_GATE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) G_PCIE40_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) LGM_GATE(LGM_GCLK_PCIE41, "g_pcie41", NULL, 0, CGU_GATE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) G_PCIE41_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) LGM_GATE(LGM_GCLK_XPCS0, "g_xpcs0", NULL, 0, CGU_GATE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) G_XPCS0_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) LGM_GATE(LGM_GCLK_XPCS1, "g_xpcs1", NULL, 0, CGU_GATE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) G_XPCS1_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) LGM_GATE(LGM_GCLK_XPCS2, "g_xpcs2", NULL, 0, CGU_GATE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) G_XPCS2_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) LGM_GATE(LGM_GCLK_XPCS3, "g_xpcs3", NULL, 0, CGU_GATE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) G_XPCS3_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) LGM_GATE(LGM_GCLK_SATA0, "g_sata0", NULL, 0, CGU_GATE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) G_SATA0_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) LGM_GATE(LGM_GCLK_SATA1, "g_sata1", NULL, 0, CGU_GATE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) G_SATA1_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) LGM_GATE(LGM_GCLK_SATA2, "g_sata2", NULL, 0, CGU_GATE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) G_SATA2_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) LGM_GATE(LGM_GCLK_SATA3, "g_sata3", NULL, 0, CGU_GATE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) G_SATA3_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) LGM_GATE(LGM_GCLK_ARCEM4, "g_arcem4", NULL, 0, CGU_GATE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) G_ARCEM4_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) LGM_GATE(LGM_GCLK_IDMAR1, "g_idmar1", NULL, 0, CGU_GATE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) G_IDMAR1_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) LGM_GATE(LGM_GCLK_IDMAT0, "g_idmat0", NULL, 0, CGU_GATE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) G_IDMAT0_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) LGM_GATE(LGM_GCLK_IDMAT1, "g_idmat1", NULL, 0, CGU_GATE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) G_IDMAT1_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) LGM_GATE(LGM_GCLK_IDMAT2, "g_idmat2", NULL, 0, CGU_GATE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) G_IDMAT2_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) LGM_GATE(LGM_GCLK_PPV4, "g_ppv4", NULL, 0, CGU_GATE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) G_PPV4_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) LGM_GATE(LGM_GCLK_GSWIPO, "g_gswipo", "switch", 0, CGU_GATE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) G_GSWIPO_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) LGM_GATE(LGM_GCLK_CQEM, "g_cqem", "switch", 0, CGU_GATE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) G_CQEM_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) LGM_GATE(LGM_GCLK_XPCS5, "g_xpcs5", NULL, 0, CGU_GATE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) G_XPCS5_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) LGM_GATE(LGM_GCLK_USB1, "g_usb1", NULL, 0, CGU_GATE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) G_USB1_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) LGM_GATE(LGM_GCLK_USB2, "g_usb2", NULL, 0, CGU_GATE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) G_USB2_SHIFT, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const struct lgm_clk_ddiv_data lgm_ddiv_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) LGM_DDIV(LGM_CLK_CML, "dd_cml", "ljpll3", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) PLL_DIV(CGU_LJPLL3_CFG0), 0, PLL_DDIV_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 3, PLL_DDIV_WIDTH, 24, 1, 29, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) LGM_DDIV(LGM_CLK_SERDES, "dd_serdes", "ljpll3", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PLL_DIV(CGU_LJPLL3_CFG0), 6, PLL_DDIV_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 9, PLL_DDIV_WIDTH, 25, 1, 28, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) LGM_DDIV(LGM_CLK_POOL, "dd_pool", "ljpll3", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PLL_DIV(CGU_LJPLL3_CFG0), 12, PLL_DDIV_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 15, PLL_DDIV_WIDTH, 26, 1, 28, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) LGM_DDIV(LGM_CLK_PTP, "dd_ptp", "ljpll3", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PLL_DIV(CGU_LJPLL3_CFG0), 18, PLL_DDIV_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 21, PLL_DDIV_WIDTH, 27, 1, 28, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) LGM_DDIV(LGM_CLK_PCIE, "dd_pcie", "ljpll4", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PLL_DIV(CGU_LJPLL4_CFG0), 0, PLL_DDIV_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 3, PLL_DDIV_WIDTH, 24, 1, 29, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int lgm_cgu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct lgm_clk_provider *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ctx = devm_kzalloc(dev, struct_size(ctx, clk_data.hws, CLK_NR_CLKS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ctx->clk_data.num = CLK_NR_CLKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ctx->membase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (IS_ERR(ctx->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return PTR_ERR(ctx->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ctx->np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ctx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) spin_lock_init(&ctx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = lgm_clk_register_plls(ctx, lgm_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ARRAY_SIZE(lgm_pll_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ret = lgm_clk_register_branches(ctx, lgm_branch_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ARRAY_SIZE(lgm_branch_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ret = lgm_clk_register_ddiv(ctx, lgm_ddiv_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ARRAY_SIZE(lgm_ddiv_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) &ctx->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static const struct of_device_id of_lgm_cgu_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { .compatible = "intel,cgu-lgm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static struct platform_driver lgm_cgu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .probe = lgm_cgu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .name = "cgu-lgm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .of_match_table = of_lgm_cgu_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) builtin_platform_driver(lgm_cgu_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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