^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: MIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * clock framework for AMD Stoney based clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2018 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_data/clk-fch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Clock Driving Strength 2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLKDRVSTR2 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Clock Control 1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MISCCLKCNTL1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Auxiliary clock1 enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OSCCLKENB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* 25Mhz auxiliary output clock freq bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OSCOUT1CLK25MHZ 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ST_CLK_48M 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ST_CLK_25M 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ST_CLK_MUX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ST_CLK_GATE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ST_MAX_CLKS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RV_CLK_48M 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RV_CLK_GATE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RV_MAX_CLKS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static struct clk_hw *hws[ST_MAX_CLKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int fch_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct fch_clk_data *fch_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) fch_data = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (!fch_data || !fch_data->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (!fch_data->is_rv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) NULL, 0, 48000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) NULL, 0, 25000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 0, fch_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "oscout1_mux", 0, fch_data->base + MISCCLKCNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "oscout1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) hws[RV_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) NULL, 0, 48000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) hws[RV_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "clk48MHz", 0, fch_data->base + MISCCLKCNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) devm_clk_hw_register_clkdev(&pdev->dev, hws[RV_CLK_GATE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "oscout1", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int fch_clk_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int i, clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct fch_clk_data *fch_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) fch_data = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) clks = fch_data->is_rv ? RV_MAX_CLKS : ST_MAX_CLKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) for (i = 0; i < clks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) clk_hw_unregister(hws[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static struct platform_driver fch_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .name = "clk-fch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .probe = fch_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .remove = fch_clk_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) builtin_platform_driver(fch_clk_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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