^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright(c) 2020 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Zhu YiXin <yixin.zhu@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Rahul Tanwar <rahul.tanwar@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __CLK_CGU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __CLK_CGU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct lgm_clk_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct lgm_clk_divider {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u8 shift_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 width_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) const struct clk_div_table *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct lgm_clk_ddiv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 shift0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 width0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 shift1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 width1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u8 shift2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u8 width2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u8 shift_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 width_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned int mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct lgm_clk_gate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) enum lgm_clk_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) CLK_TYPE_FIXED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) CLK_TYPE_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) CLK_TYPE_DIVIDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) CLK_TYPE_FIXED_FACTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) CLK_TYPE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) CLK_TYPE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * struct lgm_clk_provider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @membase: IO mem base address for CGU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @np: device node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @dev: device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @clk_data: array of hw clocks and clk number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct lgm_clk_provider {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct clk_hw_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) enum pll_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) TYPE_ROPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) TYPE_LJPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) TYPE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct lgm_clk_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) enum pll_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * struct lgm_pll_clk_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @id: platform specific id of the clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @name: name of this pll clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @parent_data: parent clock data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @num_parents: number of parents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @flags: optional flags for basic clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @type: platform type of pll.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @reg: offset of the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct lgm_pll_clk_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const struct clk_parent_data *parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) enum pll_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define LGM_PLL(_id, _name, _pdata, _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) _reg, _type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .parent_data = _pdata, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .num_parents = ARRAY_SIZE(_pdata), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .type = _type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct lgm_clk_ddiv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const struct clk_parent_data *parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned long div_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u8 shift0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 width0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u8 shift1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 width1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u8 shift_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 width_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 ex_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 ex_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define LGM_DDIV(_id, _name, _pname, _flags, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) _shft0, _wdth0, _shft1, _wdth1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) _shft_gate, _wdth_gate, _xshft, _df) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .parent_data = &(const struct clk_parent_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .fw_name = _pname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .name = _pname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .shift0 = _shft0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .width0 = _wdth0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .shift1 = _shft1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .width1 = _wdth1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .shift_gate = _shft_gate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .width_gate = _wdth_gate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .ex_shift = _xshft, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .ex_width = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .div_flags = _df, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct lgm_clk_branch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) enum lgm_clk_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) const struct clk_parent_data *parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u8 num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int mux_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u8 mux_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u8 mux_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned long mux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int mux_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int div_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u8 div_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u8 div_shift_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u8 div_width_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long div_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int div_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) const struct clk_div_table *div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int gate_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u8 gate_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned long gate_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int gate_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* clock flags definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CLOCK_FLAG_VAL_INIT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MUX_CLK_SW BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define LGM_MUX(_id, _name, _pdata, _f, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) _shift, _width, _cf, _v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .type = CLK_TYPE_MUX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .parent_data = _pdata, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .num_parents = ARRAY_SIZE(_pdata), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .flags = _f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .mux_off = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .mux_shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .mux_width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .mux_flags = _cf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .mux_val = _v, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define LGM_DIV(_id, _name, _pname, _f, _reg, _shift, _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) _shift_gate, _width_gate, _cf, _v, _dtable) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .type = CLK_TYPE_DIVIDER, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .parent_data = &(const struct clk_parent_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .fw_name = _pname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .name = _pname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .flags = _f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .div_off = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .div_shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .div_width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .div_shift_gate = _shift_gate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .div_width_gate = _width_gate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .div_flags = _cf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .div_val = _v, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .div_table = _dtable, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define LGM_GATE(_id, _name, _pname, _f, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) _shift, _cf, _v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .type = CLK_TYPE_GATE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .parent_data = &(const struct clk_parent_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .fw_name = _pname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .name = _pname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .num_parents = !_pname ? 0 : 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .flags = _f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .gate_off = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .gate_shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .gate_flags = _cf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .gate_val = _v, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define LGM_FIXED(_id, _name, _pname, _f, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) _shift, _width, _cf, _freq, _v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .type = CLK_TYPE_FIXED, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .parent_data = &(const struct clk_parent_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .fw_name = _pname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .name = _pname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .num_parents = !_pname ? 0 : 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .flags = _f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .div_off = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .div_shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .div_width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .div_flags = _cf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .div_val = _v, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .mux_flags = _freq, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define LGM_FIXED_FACTOR(_id, _name, _pname, _f, _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) _shift, _width, _cf, _v, _m, _d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .type = CLK_TYPE_FIXED_FACTOR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .parent_data = &(const struct clk_parent_data){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .fw_name = _pname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .name = _pname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .num_parents = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .flags = _f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .div_off = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .div_shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .div_width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .div_flags = _cf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .div_val = _v, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .mult = _m, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .div = _d, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static inline void lgm_set_clk_val(void __iomem *membase, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 shift, u8 width, u32 set_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 mask = (GENMASK(width - 1, 0) << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) regval = readl(membase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) regval = (regval & ~mask) | ((set_val << shift) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) writel(regval, membase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static inline u32 lgm_get_clk_val(void __iomem *membase, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u8 shift, u8 width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 mask = (GENMASK(width - 1, 0) << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) val = readl(membase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) val = (val & mask) >> shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int lgm_clk_register_branches(struct lgm_clk_provider *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) const struct lgm_clk_branch *list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned int nr_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int lgm_clk_register_plls(struct lgm_clk_provider *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) const struct lgm_pll_clk_data *list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned int nr_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) const struct lgm_clk_ddiv_data *list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int nr_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #endif /* __CLK_CGU_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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