^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 ARM Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/amba/sp810.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define to_clk_sp810_timerclken(_hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) container_of(_hw, struct clk_sp810_timerclken, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct clk_sp810;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct clk_sp810_timerclken {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct clk_sp810 *sp810;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct clk_sp810 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct clk_sp810_timerclken timerclken[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static u8 clk_sp810_timerclken_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct clk_sp810_timerclken *timerclken = to_clk_sp810_timerclken(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 val = readl(timerclken->sp810->base + SCCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return !!(val & (1 << SCCTRL_TIMERENnSEL_SHIFT(timerclken->channel)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int clk_sp810_timerclken_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct clk_sp810_timerclken *timerclken = to_clk_sp810_timerclken(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clk_sp810 *sp810 = timerclken->sp810;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 val, shift = SCCTRL_TIMERENnSEL_SHIFT(timerclken->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (WARN_ON(index > 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) spin_lock_irqsave(&sp810->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) val = readl(sp810->base + SCCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) val &= ~(1 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) val |= index << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) writel(val, sp810->base + SCCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) spin_unlock_irqrestore(&sp810->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const struct clk_ops clk_sp810_timerclken_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .get_parent = clk_sp810_timerclken_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .set_parent = clk_sp810_timerclken_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static struct clk *clk_sp810_timerclken_of_get(struct of_phandle_args *clkspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct clk_sp810 *sp810 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (WARN_ON(clkspec->args_count != 1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) clkspec->args[0] >= ARRAY_SIZE(sp810->timerclken)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return sp810->timerclken[clkspec->args[0]].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void __init clk_sp810_of_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct clk_sp810 *sp810 = kzalloc(sizeof(*sp810), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) const char *parent_names[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int num = ARRAY_SIZE(parent_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) char name[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bool deprecated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (!sp810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (of_clk_parent_fill(node, parent_names, num) != num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pr_warn("Failed to obtain parent clocks for SP810!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) kfree(sp810);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) sp810->node = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) sp810->base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) spin_lock_init(&sp810->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) init.ops = &clk_sp810_timerclken_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) init.num_parents = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) deprecated = !of_find_property(node, "assigned-clock-parents", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) for (i = 0; i < ARRAY_SIZE(sp810->timerclken); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) snprintf(name, sizeof(name), "sp810_%d_%d", instance, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) sp810->timerclken[i].sp810 = sp810;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) sp810->timerclken[i].channel = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) sp810->timerclken[i].hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * If DT isn't setting the parent, force it to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * the 1 MHz clock without going through the framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * We do this before clk_register() so that it can determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * the parent and setup the tree properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (deprecated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) init.ops->set_parent(&sp810->timerclken[i].hw, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) sp810->timerclken[i].clk = clk_register(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) &sp810->timerclken[i].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) WARN_ON(IS_ERR(sp810->timerclken[i].clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) of_clk_add_provider(node, clk_sp810_timerclken_of_get, sp810);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) instance++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) CLK_OF_DECLARE(sp810, "arm,sp810", clk_sp810_of_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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