^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Clocks for ux500 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 ST-Ericsson SA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Ulf Hansson <ulf.hansson@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __UX500_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __UX500_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct clk *clk_reg_prcc_pclk(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) resource_size_t phy_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 cg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk *clk_reg_prcc_kclk(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) resource_size_t phy_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 cg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct clk *clk_reg_prcmu_scalable(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 cg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct clk *clk_reg_prcmu_gate(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 cg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct clk *clk_reg_prcmu_scalable_rate(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 cg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clk *clk_reg_prcmu_rate(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 cg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct clk *clk_reg_prcmu_opp_gate(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 cg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 cg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct clk *clk_reg_sysctrl_gate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u16 reg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 reg_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 reg_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned long enable_delay_us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u16 reg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 reg_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 reg_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long enable_delay_us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct clk *clk_reg_sysctrl_set_parent(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) const char **parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u16 *reg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 *reg_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 *reg_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #endif /* __UX500_CLK_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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