^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Sysctrl clock implementation for ux500 platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 ST-Ericsson SA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Ulf Hansson <ulf.hansson@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/abx500/ab8500-sysctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SYSCTRL_MAX_NUM_PARENTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define to_clk_sysctrl(_hw) container_of(_hw, struct clk_sysctrl, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk_sysctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u8 parent_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u16 reg_sel[SYSCTRL_MAX_NUM_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u8 reg_mask[SYSCTRL_MAX_NUM_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 reg_bits[SYSCTRL_MAX_NUM_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned long enable_delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Sysctrl clock operations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int clk_sysctrl_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct clk_sysctrl *clk = to_clk_sysctrl(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) clk->reg_bits[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (!ret && clk->enable_delay_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) usleep_range(clk->enable_delay_us, clk->enable_delay_us +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) (clk->enable_delay_us >> 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static void clk_sysctrl_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct clk_sysctrl *clk = to_clk_sysctrl(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dev_err(clk->dev, "clk_sysctrl: %s fail to clear %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) __func__, clk_hw_get_name(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static unsigned long clk_sysctrl_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct clk_sysctrl *clk = to_clk_sysctrl(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return clk->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int clk_sysctrl_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk_sysctrl *clk = to_clk_sysctrl(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 old_index = clk->parent_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (clk->reg_sel[old_index]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ret = ab8500_sysctrl_clear(clk->reg_sel[old_index],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clk->reg_mask[old_index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (clk->reg_sel[index]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = ab8500_sysctrl_write(clk->reg_sel[index],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) clk->reg_mask[index],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clk->reg_bits[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (clk->reg_sel[old_index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ab8500_sysctrl_write(clk->reg_sel[old_index],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) clk->reg_mask[old_index],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) clk->reg_bits[old_index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) clk->parent_index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static u8 clk_sysctrl_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct clk_sysctrl *clk = to_clk_sysctrl(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return clk->parent_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct clk_ops clk_sysctrl_gate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .prepare = clk_sysctrl_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .unprepare = clk_sysctrl_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const struct clk_ops clk_sysctrl_gate_fixed_rate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .prepare = clk_sysctrl_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .unprepare = clk_sysctrl_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .recalc_rate = clk_sysctrl_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct clk_ops clk_sysctrl_set_parent_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .set_parent = clk_sysctrl_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .get_parent = clk_sysctrl_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct clk *clk_reg_sysctrl(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) const char **parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u16 *reg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u8 *reg_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 *reg_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned long enable_delay_us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const struct clk_ops *clk_sysctrl_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct clk_sysctrl *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct clk_init_data clk_sysctrl_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct clk *clk_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (!name || (num_parents > SYSCTRL_MAX_NUM_PARENTS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dev_err(dev, "clk_sysctrl: invalid arguments passed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (!clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* set main clock registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) clk->reg_sel[0] = reg_sel[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) clk->reg_bits[0] = reg_bits[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) clk->reg_mask[0] = reg_mask[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* handle clocks with more than one parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) for (i = 1; i < num_parents; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) clk->reg_sel[i] = reg_sel[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) clk->reg_bits[i] = reg_bits[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) clk->reg_mask[i] = reg_mask[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) clk->parent_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) clk->rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) clk->enable_delay_us = enable_delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) clk->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) clk_sysctrl_init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clk_sysctrl_init.ops = clk_sysctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) clk_sysctrl_init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) clk_sysctrl_init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) clk_sysctrl_init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) clk->hw.init = &clk_sysctrl_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) clk_reg = devm_clk_register(clk->dev, &clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (IS_ERR(clk_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dev_err(dev, "clk_sysctrl: clk_register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return clk_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct clk *clk_reg_sysctrl_gate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u16 reg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 reg_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u8 reg_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned long enable_delay_us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) const char **parent_names = (parent_name ? &parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 num_parents = (parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return clk_reg_sysctrl(dev, name, parent_names, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ®_sel, ®_mask, ®_bits, 0, enable_delay_us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) flags, &clk_sysctrl_gate_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u16 reg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 reg_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 reg_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned long enable_delay_us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) const char **parent_names = (parent_name ? &parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 num_parents = (parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return clk_reg_sysctrl(dev, name, parent_names, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ®_sel, ®_mask, ®_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) rate, enable_delay_us, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) &clk_sysctrl_gate_fixed_rate_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct clk *clk_reg_sysctrl_set_parent(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) const char **parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u16 *reg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u8 *reg_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u8 *reg_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return clk_reg_sysctrl(dev, name, parent_names, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) reg_sel, reg_mask, reg_bits, 0, 0, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) &clk_sysctrl_set_parent_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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