^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PRCC clock implementation for ux500 platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 ST-Ericsson SA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Ulf Hansson <ulf.hansson@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PRCC_PCKEN 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PRCC_PCKDIS 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PRCC_KCKEN 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PRCC_KCKDIS 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PRCC_PCKSR 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PRCC_KCKSR 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define to_clk_prcc(_hw) container_of(_hw, struct clk_prcc, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct clk_prcc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 cg_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int is_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* PRCC clock operations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int clk_prcc_pclk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct clk_prcc *clk = to_clk_prcc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) writel(clk->cg_sel, (clk->base + PRCC_PCKEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) while (!(readl(clk->base + PRCC_PCKSR) & clk->cg_sel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) clk->is_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void clk_prcc_pclk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clk_prcc *clk = to_clk_prcc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) writel(clk->cg_sel, (clk->base + PRCC_PCKDIS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) clk->is_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int clk_prcc_kclk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct clk_prcc *clk = to_clk_prcc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) writel(clk->cg_sel, (clk->base + PRCC_KCKEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) while (!(readl(clk->base + PRCC_KCKSR) & clk->cg_sel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) clk->is_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void clk_prcc_kclk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct clk_prcc *clk = to_clk_prcc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) writel(clk->cg_sel, (clk->base + PRCC_KCKDIS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) clk->is_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int clk_prcc_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct clk_prcc *clk = to_clk_prcc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return clk->is_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct clk_ops clk_prcc_pclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .enable = clk_prcc_pclk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .disable = clk_prcc_pclk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .is_enabled = clk_prcc_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const struct clk_ops clk_prcc_kclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .enable = clk_prcc_kclk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .disable = clk_prcc_kclk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .is_enabled = clk_prcc_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static struct clk *clk_reg_prcc(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) resource_size_t phy_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 cg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const struct clk_ops *clk_prcc_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct clk_prcc *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct clk_init_data clk_prcc_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct clk *clk_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (!name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pr_err("clk_prcc: %s invalid arguments passed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clk = kzalloc(sizeof(*clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (!clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) clk->base = ioremap(phy_base, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (!clk->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) goto free_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) clk->cg_sel = cg_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) clk->is_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) clk_prcc_init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) clk_prcc_init.ops = clk_prcc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) clk_prcc_init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) clk_prcc_init.parent_names = (parent_name ? &parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) clk_prcc_init.num_parents = (parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) clk->hw.init = &clk_prcc_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clk_reg = clk_register(NULL, &clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (IS_ERR_OR_NULL(clk_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) goto unmap_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return clk_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unmap_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) iounmap(clk->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) free_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) kfree(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pr_err("clk_prcc: %s failed to register clk\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct clk *clk_reg_prcc_pclk(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) resource_size_t phy_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 cg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return clk_reg_prcc(name, parent_name, phy_base, cg_sel, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) &clk_prcc_pclk_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct clk *clk_reg_prcc_kclk(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) resource_size_t phy_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 cg_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return clk_reg_prcc(name, parent_name, phy_base, cg_sel, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) &clk_prcc_kclk_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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