^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * abx500 clock implementation for ux500 platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 ST-Ericsson SA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Ulf Hansson <ulf.hansson@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/abx500/ab8500.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mfd/abx500/ab8500-sysctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/clock/ste-ab8500.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "clk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AB8500_NUM_CLKS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static struct clk *ab8500_clks[AB8500_NUM_CLKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static struct clk_onecell_data ab8500_clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Clock definitions for ab8500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static int ab8500_reg_clks(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) const char *intclk_parents[] = {"ab8500_sysclk", "ulpclk"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u16 intclk_reg_sel[] = {0 , AB8500_SYSULPCLKCTRL1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u8 intclk_reg_mask[] = {0 , AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 intclk_reg_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 0 ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) (1 << AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Enable SWAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ret = ab8500_sysctrl_set(AB8500_SWATCTRL, AB8500_SWATCTRL_SWATENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* ab8500_sysclk2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk2", "ab8500_sysclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ab8500_clks[AB8500_SYSCLK_BUF2] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* ab8500_sysclk3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk3", "ab8500_sysclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ab8500_clks[AB8500_SYSCLK_BUF3] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* ab8500_sysclk4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk4", "ab8500_sysclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ab8500_clks[AB8500_SYSCLK_BUF4] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* ab_ulpclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) clk = clk_reg_sysctrl_gate_fixed_rate(dev, "ulpclk", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 38400000, 9000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ab8500_clks[AB8500_SYSCLK_ULP] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* ab8500_intclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clk = clk_reg_sysctrl_set_parent(dev , "intclk", intclk_parents, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) intclk_reg_sel, intclk_reg_mask, intclk_reg_bits, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ab8500_clks[AB8500_SYSCLK_INT] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* ab8500_audioclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) clk = clk_reg_sysctrl_gate(dev , "audioclk", "intclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_AUDIOCLKENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) AB8500_SYSULPCLKCTRL1_AUDIOCLKENA, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ab8500_clks[AB8500_SYSCLK_AUDIO] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ab8500_clk_data.clks = ab8500_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ab8500_clk_data.clk_num = ARRAY_SIZE(ab8500_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) of_clk_add_provider(np, of_clk_src_onecell_get, &ab8500_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dev_info(dev, "registered clocks for ab850x\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int abx500_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct ab8500 *parent = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (is_ab8500(parent) || is_ab8505(parent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ret = ab8500_reg_clks(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dev_err(&pdev->dev, "non supported plf id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct of_device_id abx500_clk_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { .compatible = "stericsson,ab8500-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct platform_driver abx500_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .name = "abx500-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .of_match_table = abx500_clk_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .probe = abx500_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int __init abx500_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return platform_driver_register(&abx500_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) arch_initcall(abx500_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MODULE_AUTHOR("Ulf Hansson <ulf.hansson@linaro.org");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MODULE_DESCRIPTION("ABX500 clk driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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