^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __CLK_UNIPHIER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __CLK_UNIPHIER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) struct clk_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) struct device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define UNIPHIER_CLK_CPUGEAR_MAX_PARENTS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define UNIPHIER_CLK_MUX_MAX_PARENTS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) enum uniphier_clk_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) UNIPHIER_CLK_TYPE_CPUGEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) UNIPHIER_CLK_TYPE_FIXED_FACTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) UNIPHIER_CLK_TYPE_FIXED_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) UNIPHIER_CLK_TYPE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) UNIPHIER_CLK_TYPE_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct uniphier_clk_cpugear_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) const char *parent_names[UNIPHIER_CLK_CPUGEAR_MAX_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned int regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct uniphier_clk_fixed_factor_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned int mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct uniphier_clk_fixed_rate_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long fixed_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct uniphier_clk_gate_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct uniphier_clk_mux_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) const char *parent_names[UNIPHIER_CLK_MUX_MAX_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int masks[UNIPHIER_CLK_MUX_MAX_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int vals[UNIPHIER_CLK_MUX_MAX_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct uniphier_clk_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) enum uniphier_clk_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct uniphier_clk_cpugear_data cpugear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct uniphier_clk_fixed_factor_data factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct uniphier_clk_fixed_rate_data rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct uniphier_clk_gate_data gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct uniphier_clk_mux_data mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) } data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define UNIPHIER_CLK_CPUGEAR(_name, _idx, _regbase, _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) _num_parents, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .name = (_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .type = UNIPHIER_CLK_TYPE_CPUGEAR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .idx = (_idx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .data.cpugear = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .parent_names = { __VA_ARGS__ }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .num_parents = (_num_parents), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .regbase = (_regbase), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .mask = (_mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define UNIPHIER_CLK_FACTOR(_name, _idx, _parent, _mult, _div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .name = (_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .idx = (_idx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .data.factor = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .parent_name = (_parent), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .mult = (_mult), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .div = (_div), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .name = (_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .type = UNIPHIER_CLK_TYPE_GATE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .idx = (_idx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .data.gate = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .parent_name = (_parent), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .reg = (_reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .bit = (_bit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define UNIPHIER_CLK_DIV(parent, div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) UNIPHIER_CLK_FACTOR(parent "/" #div, -1, parent, 1, div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define UNIPHIER_CLK_DIV2(parent, div0, div1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) UNIPHIER_CLK_DIV(parent, div0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) UNIPHIER_CLK_DIV(parent, div1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) UNIPHIER_CLK_DIV2(parent, div0, div1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) UNIPHIER_CLK_DIV(parent, div2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) UNIPHIER_CLK_DIV2(parent, div0, div1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) UNIPHIER_CLK_DIV2(parent, div2, div3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct clk_hw *uniphier_clk_register_cpugear(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const struct uniphier_clk_cpugear_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct clk_hw *uniphier_clk_register_fixed_factor(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const struct uniphier_clk_fixed_factor_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct clk_hw *uniphier_clk_register_fixed_rate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) const struct uniphier_clk_fixed_rate_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct clk_hw *uniphier_clk_register_gate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) const struct uniphier_clk_gate_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct clk_hw *uniphier_clk_register_mux(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const struct uniphier_clk_mux_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) extern const struct uniphier_clk_data uniphier_ld4_sys_clk_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) extern const struct uniphier_clk_data uniphier_pro4_sys_clk_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) extern const struct uniphier_clk_data uniphier_sld8_sys_clk_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) extern const struct uniphier_clk_data uniphier_pro5_sys_clk_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) extern const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) extern const struct uniphier_clk_data uniphier_ld4_mio_clk_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #endif /* __CLK_UNIPHIER_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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