^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "clk-uniphier.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define UNIPHIER_LD4_SYS_CLK_SD \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define UNIPHIER_PRO5_SYS_CLK_SD \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define UNIPHIER_LD20_SYS_CLK_SD \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define UNIPHIER_LD4_SYS_CLK_NAND(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define UNIPHIER_PRO5_SYS_CLK_NAND(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UNIPHIER_LD11_SYS_CLK_NAND(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define UNIPHIER_SYS_CLK_NAND_4X(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) UNIPHIER_CLK_FACTOR("nand-4x", (idx), "nand", 4, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define UNIPHIER_LD11_SYS_CLK_EMMC(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UNIPHIER_LD4_SYS_CLK_STDMAC(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define UNIPHIER_LD11_SYS_CLK_HSC(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) UNIPHIER_CLK_GATE("hsc", (idx), NULL, 0x210c, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define UNIPHIER_PRO4_SYS_CLK_AIO(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 8), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define UNIPHIER_PRO5_SYS_CLK_AIO(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 12), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define UNIPHIER_LD11_SYS_CLK_AIO(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define UNIPHIER_LD11_SYS_CLK_EVEA(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define UNIPHIER_LD11_SYS_CLK_EXIV(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define UNIPHIER_PRO4_SYS_CLK_ETHER(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x2104, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define UNIPHIER_LD11_SYS_CLK_ETHER(idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x210c, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) UNIPHIER_LD4_SYS_CLK_NAND(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) UNIPHIER_SYS_CLK_NAND_4X(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) UNIPHIER_LD4_SYS_CLK_SD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) UNIPHIER_CLK_FACTOR("spi", 1, "spll", 1, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) UNIPHIER_LD4_SYS_CLK_NAND(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) UNIPHIER_SYS_CLK_NAND_4X(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) UNIPHIER_LD4_SYS_CLK_SD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) UNIPHIER_PRO4_SYS_CLK_ETHER(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) UNIPHIER_CLK_GATE("ether-phy", 10, "ref", 0x2260, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) UNIPHIER_CLK_FACTOR("usb30-hsphy0", 16, "upll", 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) UNIPHIER_CLK_FACTOR("usb30-ssphy0", 17, "ref", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) UNIPHIER_CLK_FACTOR("usb31-ssphy0", 20, "ref", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x2104, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) UNIPHIER_PRO4_SYS_CLK_AIO(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) UNIPHIER_LD4_SYS_CLK_NAND(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) UNIPHIER_SYS_CLK_NAND_4X(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) UNIPHIER_LD4_SYS_CLK_SD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125), /* 2949.12 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) UNIPHIER_PRO5_SYS_CLK_NAND(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) UNIPHIER_SYS_CLK_NAND_4X(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) UNIPHIER_PRO5_SYS_CLK_SD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x2108, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) UNIPHIER_PRO5_SYS_CLK_AIO(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) UNIPHIER_PRO5_SYS_CLK_NAND(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) UNIPHIER_SYS_CLK_NAND_4X(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) UNIPHIER_PRO5_SYS_CLK_SD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) UNIPHIER_PRO4_SYS_CLK_ETHER(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, RLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* GIO is always clock-enabled: no function for 0x2104 bit6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* The document mentions 0x2104 bit 18, but not functional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x2104, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) UNIPHIER_CLK_FACTOR("usb30-ssphy0", 17, "ref", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) UNIPHIER_CLK_FACTOR("usb30-ssphy1", 18, "ref", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x2104, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) UNIPHIER_CLK_FACTOR("usb31-ssphy0", 21, "ref", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) UNIPHIER_PRO5_SYS_CLK_AIO(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 392, 5), /* 1960 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* 1600 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1), /* 2000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) UNIPHIER_LD11_SYS_CLK_NAND(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) UNIPHIER_SYS_CLK_NAND_4X(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) UNIPHIER_LD11_SYS_CLK_EMMC(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Index 5 reserved for eMMC PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) UNIPHIER_LD11_SYS_CLK_ETHER(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) UNIPHIER_LD11_SYS_CLK_HSC(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) UNIPHIER_LD11_SYS_CLK_AIO(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) UNIPHIER_LD11_SYS_CLK_EVEA(41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) UNIPHIER_LD11_SYS_CLK_EXIV(42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* CPU gears */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) UNIPHIER_CLK_DIV3("spll", 3, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Note: both gear1 and gear4 are spll/4. This is not a bug. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "cpll/2", "spll/4", "cpll/3", "spll/3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "spll/4", "spll/8", "cpll/4", "cpll/8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "mpll/2", "spll/4", "mpll/3", "spll/3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "spll/4", "spll/8", "mpll/4", "mpll/8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 88, 1), /* ARM: 2200 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) UNIPHIER_CLK_FACTOR("gppll", -1, "ref", 52, 1), /* Mali: 1300 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* Codec: 1600 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2200 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5), /* 2520 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) UNIPHIER_LD11_SYS_CLK_NAND(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) UNIPHIER_SYS_CLK_NAND_4X(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) UNIPHIER_LD11_SYS_CLK_EMMC(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Index 5 reserved for eMMC PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) UNIPHIER_LD20_SYS_CLK_SD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) UNIPHIER_LD11_SYS_CLK_ETHER(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) UNIPHIER_LD11_SYS_CLK_HSC(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* GIO is always clock-enabled: no function for 0x210c bit5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * We do not use bit 15 here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) UNIPHIER_CLK_GATE("usb30-hsphy1", 17, NULL, 0x210c, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) UNIPHIER_CLK_FACTOR("usb30-ssphy0", 18, "ref", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) UNIPHIER_CLK_FACTOR("usb30-ssphy1", 19, "ref", 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) UNIPHIER_LD11_SYS_CLK_AIO(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) UNIPHIER_LD11_SYS_CLK_EVEA(41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) UNIPHIER_LD11_SYS_CLK_EXIV(42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* CPU gears */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) UNIPHIER_CLK_CPUGEAR("cpu-ca72", 32, 0x8000, 0xf, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "cpll/2", "spll/2", "cpll/3", "spll/3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "spll/4", "spll/8", "cpll/4", "cpll/8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "cpll/2", "spll/2", "cpll/3", "spll/3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "spll/4", "spll/8", "cpll/4", "cpll/8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "s2pll/2", "spll/2", "s2pll/3", "spll/3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 104, 1), /* ARM: 2600 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2400 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) UNIPHIER_LD20_SYS_CLK_SD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) UNIPHIER_LD11_SYS_CLK_NAND(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) UNIPHIER_SYS_CLK_NAND_4X(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) UNIPHIER_LD11_SYS_CLK_EMMC(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) UNIPHIER_CLK_GATE("ether0", 6, NULL, 0x210c, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) UNIPHIER_CLK_GATE("ether1", 7, NULL, 0x210c, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4), /* =GIO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5), /* =GIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6), /* =GIO1-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) UNIPHIER_CLK_GATE("usb30-ssphy0", 17, NULL, 0x210c, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) UNIPHIER_CLK_GATE("usb30-ssphy1", 18, NULL, 0x210c, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x210c, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) UNIPHIER_CLK_GATE("usb31-ssphy0", 21, NULL, 0x210c, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* CPU gears */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "cpll/2", "spll/2", "cpll/3", "spll/3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "spll/4", "spll/8", "cpll/4", "cpll/8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "s2pll/2", "spll/2", "s2pll/3", "spll/3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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