Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2016 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clk-uniphier.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct uniphier_clk_gate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define to_uniphier_clk_gate(_hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 				container_of(_hw, struct uniphier_clk_gate, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static int uniphier_clk_gate_endisable(struct clk_hw *hw, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	return regmap_write_bits(gate->regmap, gate->reg, BIT(gate->bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 				 enable ? BIT(gate->bit) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int uniphier_clk_gate_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	return uniphier_clk_gate_endisable(hw, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void uniphier_clk_gate_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	if (uniphier_clk_gate_endisable(hw, 0) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		pr_warn("failed to disable clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int uniphier_clk_gate_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	if (regmap_read(gate->regmap, gate->reg, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		pr_warn("is_enabled() may return wrong result\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	return !!(val & BIT(gate->bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const struct clk_ops uniphier_clk_gate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	.enable = uniphier_clk_gate_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	.disable = uniphier_clk_gate_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	.is_enabled = uniphier_clk_gate_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct clk_hw *uniphier_clk_register_gate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 					  struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 					  const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 				const struct uniphier_clk_gate_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	struct uniphier_clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	init.ops = &uniphier_clk_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	init.flags = data->parent_name ? CLK_SET_RATE_PARENT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	init.parent_names = data->parent_name ? &data->parent_name : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	init.num_parents = data->parent_name ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	gate->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	gate->reg = data->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	gate->bit = data->bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	gate->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	ret = devm_clk_hw_register(dev, &gate->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 		return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 	return &gate->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }