Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2016 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clk-uniphier.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct clk_hw *uniphier_clk_register_fixed_rate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 						const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 				const struct uniphier_clk_fixed_rate_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	struct clk_fixed_rate *fixed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	/* allocate fixed-rate clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	if (!fixed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	init.ops = &clk_fixed_rate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	init.parent_names = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	fixed->fixed_rate = data->fixed_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	fixed->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	ret = devm_clk_hw_register(dev, &fixed->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	return &fixed->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }