^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* FAPLL Control Register PLL_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FAPLL_MAIN_MULT_N_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FAPLL_MAIN_DIV_P_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FAPLL_MAIN_LOCK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FAPLL_MAIN_PLLEN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FAPLL_MAIN_BP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FAPLL_MAIN_LOC_CTL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FAPLL_MAIN_MAX_MULT_N 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FAPLL_MAIN_MAX_DIV_P 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FAPLL_MAIN_CLEAR_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ((FAPLL_MAIN_MAX_MULT_N << FAPLL_MAIN_MULT_N_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) (FAPLL_MAIN_DIV_P_SHIFT << FAPLL_MAIN_DIV_P_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) FAPLL_MAIN_LOC_CTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* FAPLL powerdown register PWD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FAPLL_PWD_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MAX_FAPLL_OUTPUTS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FAPLL_MAX_RETRIES 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define to_fapll(_hw) container_of(_hw, struct fapll_data, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define to_synth(_hw) container_of(_hw, struct fapll_synth, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* The bypass bit is inverted on the ddr_pll.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define fapll_is_ddr_pll(va) (((u32)(va) & 0xffff) == 0x0440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * and the audio_pll_clk1 synthesizer is hardwared to 32KiHz output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define is_ddr_pll_clk1(va) (((u32)(va) & 0xffff) == 0x044c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define is_audio_pll_clk1(va) (((u32)(va) & 0xffff) == 0x04a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Synthesizer divider register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SYNTH_LDMDIV1 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Synthesizer frequency register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SYNTH_LDFREQ BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SYNTH_PHASE_K 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SYNTH_MAX_INT_DIV 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SYNTH_MAX_DIV_M 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct fapll_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct clk *clk_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct clk *clk_bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct clk_onecell_data outputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) bool bypass_bit_inverted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct fapll_synth {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct fapll_data *fd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void __iomem *freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void __iomem *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct clk *clk_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static bool ti_fapll_clock_is_bypass(struct fapll_data *fd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 v = readl_relaxed(fd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (fd->bypass_bit_inverted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return !(v & FAPLL_MAIN_BP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return !!(v & FAPLL_MAIN_BP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void ti_fapll_set_bypass(struct fapll_data *fd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 v = readl_relaxed(fd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (fd->bypass_bit_inverted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) v &= ~FAPLL_MAIN_BP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) v |= FAPLL_MAIN_BP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) writel_relaxed(v, fd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void ti_fapll_clear_bypass(struct fapll_data *fd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 v = readl_relaxed(fd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (fd->bypass_bit_inverted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) v |= FAPLL_MAIN_BP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) v &= ~FAPLL_MAIN_BP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel_relaxed(v, fd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int ti_fapll_wait_lock(struct fapll_data *fd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int retries = FAPLL_MAX_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) while ((v = readl_relaxed(fd->base))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (v & FAPLL_MAIN_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (retries-- <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pr_err("%s failed to lock\n", fd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int ti_fapll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct fapll_data *fd = to_fapll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 v = readl_relaxed(fd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) v |= FAPLL_MAIN_PLLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) writel_relaxed(v, fd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ti_fapll_wait_lock(fd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void ti_fapll_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct fapll_data *fd = to_fapll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 v = readl_relaxed(fd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) v &= ~FAPLL_MAIN_PLLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) writel_relaxed(v, fd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int ti_fapll_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct fapll_data *fd = to_fapll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 v = readl_relaxed(fd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return v & FAPLL_MAIN_PLLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct fapll_data *fd = to_fapll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 fapll_n, fapll_p, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ti_fapll_clock_is_bypass(fd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* PLL pre-divider is P and multiplier is N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) v = readl_relaxed(fd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) fapll_p = (v >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (fapll_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) do_div(rate, fapll_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) fapll_n = v >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (fapll_n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) rate *= fapll_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static u8 ti_fapll_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct fapll_data *fd = to_fapll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (ti_fapll_clock_is_bypass(fd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int ti_fapll_set_div_mult(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 *pre_div_p, u32 *mult_n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * So far no luck getting decent clock with PLL divider,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * PLL does not seem to lock and the signal does not look
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * right. It seems the divider can only be used together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * with the multiplier?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (rate < parent_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pr_warn("FAPLL main divider rates unsupported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *mult_n = rate / parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (*mult_n > FAPLL_MAIN_MAX_MULT_N)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) *pre_div_p = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 pre_div_p, mult_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) error = ti_fapll_set_div_mult(rate, *parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) &pre_div_p, &mult_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) rate = *parent_rate / pre_div_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) rate *= mult_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int ti_fapll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct fapll_data *fd = to_fapll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 pre_div_p, mult_n, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) error = ti_fapll_set_div_mult(rate, parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) &pre_div_p, &mult_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ti_fapll_set_bypass(fd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) v = readl_relaxed(fd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) v &= ~FAPLL_MAIN_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) v |= pre_div_p << FAPLL_MAIN_DIV_P_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) v |= mult_n << FAPLL_MAIN_MULT_N_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) writel_relaxed(v, fd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (ti_fapll_is_enabled(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ti_fapll_wait_lock(fd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ti_fapll_clear_bypass(fd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const struct clk_ops ti_fapll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .enable = ti_fapll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .disable = ti_fapll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .is_enabled = ti_fapll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .recalc_rate = ti_fapll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .get_parent = ti_fapll_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .round_rate = ti_fapll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .set_rate = ti_fapll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int ti_fapll_synth_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct fapll_synth *synth = to_synth(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) v &= ~(1 << synth->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static void ti_fapll_synth_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct fapll_synth *synth = to_synth(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) v |= 1 << synth->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int ti_fapll_synth_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct fapll_synth *synth = to_synth(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return !(v & (1 << synth->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * See dm816x TRM chapter 1.10.3 Flying Adder PLL fore more info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct fapll_synth *synth = to_synth(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 synth_div_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!synth->div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * PLL in bypass sets the synths in bypass mode too. The PLL rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * can be also be set to 27MHz, so we can't use parent_rate to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * check for bypass mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (ti_fapll_clock_is_bypass(synth->fd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * Synth frequency integer and fractional divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Note that the phase output K is 8, so the result needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * to be multiplied by SYNTH_PHASE_K.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (synth->freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 v, synth_int_div, synth_frac_div, synth_div_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) v = readl_relaxed(synth->freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) synth_int_div = (v >> 24) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) synth_frac_div = v & 0xffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) synth_div_freq = (synth_int_div * 10000000) + synth_frac_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) rate *= 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) do_div(rate, synth_div_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rate *= SYNTH_PHASE_K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Synth post-divider M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return DIV_ROUND_UP_ULL(rate, synth_div_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static unsigned long ti_fapll_synth_get_frac_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct fapll_synth *synth = to_synth(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned long current_rate, frac_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u32 post_div_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) current_rate = ti_fapll_synth_recalc_rate(hw, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) frac_rate = current_rate * post_div_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return frac_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u32 post_div_m, synth_int_div = 0, synth_frac_div = 0, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) post_div_m = DIV_ROUND_UP_ULL((u64)parent_rate * SYNTH_PHASE_K, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) post_div_m = post_div_m / SYNTH_MAX_INT_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (post_div_m > SYNTH_MAX_DIV_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (!post_div_m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) post_div_m = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) for (; post_div_m < SYNTH_MAX_DIV_M; post_div_m++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) synth_int_div = DIV_ROUND_UP_ULL((u64)parent_rate *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) SYNTH_PHASE_K *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) rate * post_div_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) synth_frac_div = synth_int_div % 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) synth_int_div /= 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (synth_int_div <= SYNTH_MAX_INT_DIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (synth_int_div > SYNTH_MAX_INT_DIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) v = readl_relaxed(synth->freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) v &= ~0x1fffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) v |= (synth_int_div & SYNTH_MAX_INT_DIV) << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) v |= (synth_frac_div & 0xffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) v |= SYNTH_LDFREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) writel_relaxed(v, synth->freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return post_div_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static long ti_fapll_synth_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct fapll_synth *synth = to_synth(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct fapll_data *fd = synth->fd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned long r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Only post divider m available with no fractional divider? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (!synth->freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned long frac_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 synth_post_div_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) frac_rate = ti_fapll_synth_get_frac_rate(hw, *parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) synth_post_div_m = DIV_ROUND_UP(frac_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) r = DIV_ROUND_UP(frac_rate, synth_post_div_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) r = *parent_rate * SYNTH_PHASE_K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (rate > r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) r = DIV_ROUND_UP_ULL(r, SYNTH_MAX_INT_DIV * SYNTH_MAX_DIV_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (rate < r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) r = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int ti_fapll_synth_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct fapll_synth *synth = to_synth(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct fapll_data *fd = synth->fd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned long frac_rate, post_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u32 post_div_m = 0, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Produce the rate with just post divider M? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) frac_rate = ti_fapll_synth_get_frac_rate(hw, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (frac_rate < rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!synth->freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) post_div_m = DIV_ROUND_UP(frac_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (post_div_m && (post_div_m <= SYNTH_MAX_DIV_M))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) post_rate = DIV_ROUND_UP(frac_rate, post_div_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!synth->freq && !post_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Need to recalculate the fractional divider? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if ((post_rate != rate) && synth->freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) post_div_m = ti_fapll_synth_set_frac_rate(synth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) v = readl_relaxed(synth->div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) v &= ~SYNTH_MAX_DIV_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) v |= post_div_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) v |= SYNTH_LDMDIV1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) writel_relaxed(v, synth->div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const struct clk_ops ti_fapll_synt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .enable = ti_fapll_synth_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .disable = ti_fapll_synth_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .is_enabled = ti_fapll_synth_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .recalc_rate = ti_fapll_synth_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .round_rate = ti_fapll_synth_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .set_rate = ti_fapll_synth_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) void __iomem *freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) void __iomem *div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) const char *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct clk *pll_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct clk_init_data *init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct fapll_synth *synth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct clk *clk = ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) init = kzalloc(sizeof(*init), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (!init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) init->ops = &ti_fapll_synt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) init->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) init->parent_names = &parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) init->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) synth = kzalloc(sizeof(*synth), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (!synth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) synth->fd = fd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) synth->index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) synth->freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) synth->div = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) synth->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) synth->hw.init = init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) synth->clk_pll = pll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) clk = clk_register(NULL, &synth->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) pr_err("failed to register clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) kfree(synth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) kfree(init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static void __init ti_fapll_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct fapll_data *fd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct clk_init_data *init = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) const char *parent_name[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct clk *pll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) fd = kzalloc(sizeof(*fd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (!fd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) fd->outputs.clks = kzalloc(sizeof(struct clk *) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MAX_FAPLL_OUTPUTS + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (!fd->outputs.clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) init = kzalloc(sizeof(*init), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (!init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) init->ops = &ti_fapll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) init->name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) init->num_parents = of_clk_get_parent_count(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (init->num_parents != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) pr_err("%pOFn must have two parents\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) of_clk_parent_fill(node, parent_name, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) init->parent_names = parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) fd->clk_ref = of_clk_get(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (IS_ERR(fd->clk_ref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) pr_err("%pOFn could not get clk_ref\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) fd->clk_bypass = of_clk_get(node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (IS_ERR(fd->clk_bypass)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) pr_err("%pOFn could not get clk_bypass\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) fd->base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (!fd->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pr_err("%pOFn could not get IO base\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (fapll_is_ddr_pll(fd->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) fd->bypass_bit_inverted = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) fd->name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) fd->hw.init = init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* Register the parent PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) pll_clk = clk_register(NULL, &fd->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (IS_ERR(pll_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) fd->outputs.clks[0] = pll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) fd->outputs.clk_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * Set up the child synthesizers starting at index 1 as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * PLL output is at index 0. We need to check the clock-indices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * for numbering in case there are holes in the synth mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * and then probe the synth register to see if it has a FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * register available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) for (i = 0; i < MAX_FAPLL_OUTPUTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) const char *output_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) void __iomem *freq, *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct clk *synth_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int output_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (of_property_read_string_index(node, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) i, &output_name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (of_property_read_u32_index(node, "clock-indices", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) &output_instance))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) output_instance = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) freq = fd->base + (output_instance * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) div = freq + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* Check for hardwired audio_pll_clk1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (is_audio_pll_clk1(freq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) freq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) div = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Does the synthesizer have a FREQ register? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) v = readl_relaxed(freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (!v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) freq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) output_name, node->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) pll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (IS_ERR(synth_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) fd->outputs.clks[output_instance] = synth_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) fd->outputs.clk_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) clk_register_clkdev(synth_clk, output_name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Register the child synthesizers as the FAPLL outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) of_clk_add_provider(node, of_clk_src_onecell_get, &fd->outputs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* Add clock alias for the outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) kfree(init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) iounmap(fd->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (fd->clk_bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) clk_put(fd->clk_bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (fd->clk_ref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) clk_put(fd->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) kfree(fd->outputs.clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) kfree(fd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) kfree(init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) CLK_OF_DECLARE(ti_fapll_clock, "ti,dm816-fapll-clock", ti_fapll_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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