^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP4-specific DPLL control functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Rajendra Nayak
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * can supported when using the DPLL low-power mode. Frequencies are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Status, and Low-Power Operation Mode".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OMAP4_DPLL_LP_FINT_MAX 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OMAP4_DPLL_LP_FOUT_MAX 100000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Bitfield declarations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP4430_DPLL_REGM4XEN_MASK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Static rate multiplier for OMAP4 REGM4XEN clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP4430_REGM4XEN_MULT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (!clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) mask = clk->flags & CLOCK_CLKOUTX2 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Clear the bit to allow gatectrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) v &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (!clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) mask = clk->flags & CLOCK_CLKOUTX2 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Set the bit to deny gatectrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) v |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .allow_idle = omap4_dpllmx_allow_gatectrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .deny_idle = omap4_dpllmx_deny_gatectrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @dd: pointer to the dpll data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Calculates if low-power mode can be enabled based upon the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * multiplier and divider values calculated. If low-power mode can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * enabled, then the bit to enable low-power mode is stored in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * last_rounded_lpmode variable. This implementation is based upon the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * criteria for enabling low-power mode as described in the OMAP4430/60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Operation Mode".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void omap4_dpll_lpmode_recalc(struct dpll_data *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) long fint, fout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) fint = clk_hw_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) fout = fint * dd->last_rounded_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dd->last_rounded_lpmode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dd->last_rounded_lpmode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @clk: struct clk * of the DPLL to compute the rate for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Compute the output rate for the OMAP4 DPLL represented by @clk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Takes the REGM4XEN bit into consideration, which is needed for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * upon success, or 0 upon error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct clk_hw_omap *clk = to_clk_hw_omap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct dpll_data *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (!clk || !clk->dpll_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dd = clk->dpll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) rate = omap2_get_dpll_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* regm4xen adds a multiplier of 4 to DPLL calculations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (v & OMAP4430_DPLL_REGM4XEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) rate *= OMAP4430_REGM4XEN_MULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @clk: struct clk * of the DPLL to round a rate for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @target_rate: the desired rate of the DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Compute the rate that would be programmed into the DPLL hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * for @clk if set_rate() were to be provided with the rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @target_rate. Takes the REGM4XEN bit into consideration, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * needed for the OMAP4 ABE DPLL. Returns the rounded rate (before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * ~0 if an error occurred in omap2_dpll_round_rate().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned long target_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct clk_hw_omap *clk = to_clk_hw_omap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct dpll_data *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) long r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (!clk || !clk->dpll_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dd = clk->dpll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dd->last_rounded_m4xen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * First try to compute the DPLL configuration for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * target rate without using the 4X multiplier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) r = omap2_dpll_round_rate(hw, target_rate, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (r != ~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * If we did not find a valid DPLL configuration, try again, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * this time see if using the 4X multiplier can help. Enabling the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * 4X multiplier is equivalent to dividing the target rate by 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (r == ~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dd->last_rounded_m4xen = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) omap4_dpll_lpmode_recalc(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return dd->last_rounded_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @hw: pointer to the clock to determine rate for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @req: target rate request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * Determines which DPLL mode to use for reaching a desired rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Checks whether the DPLL shall be in bypass or locked mode, and if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * locked, calculates the M,N values for the DPLL via round-rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Returns 0 on success and a negative error value otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct clk_hw_omap *clk = to_clk_hw_omap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct dpll_data *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!req->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dd = clk->dpll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) req->best_parent_hw = dd->clk_bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) req->rate = omap4_dpll_regm4xen_round_rate(hw, req->rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) &req->best_parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) req->best_parent_hw = dd->clk_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) req->best_parent_rate = req->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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