^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * OMAP DPLL clock support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Tero Kristo <t-kristo@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #undef pr_fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define pr_fmt(fmt) "%s: " fmt, __func__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) defined(CONFIG_SOC_DRA7XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const struct clk_ops dpll_m4xen_ck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .enable = &omap3_noncore_dpll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .disable = &omap3_noncore_dpll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .recalc_rate = &omap4_dpll_regm4xen_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .round_rate = &omap4_dpll_regm4xen_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .set_rate = &omap3_noncore_dpll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .set_parent = &omap3_noncore_dpll_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .determine_rate = &omap4_dpll_regm4xen_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .get_parent = &omap2_init_dpll_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .save_context = &omap3_core_dpll_save_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .restore_context = &omap3_core_dpll_restore_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const struct clk_ops dpll_m4xen_ck_ops = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const struct clk_ops dpll_core_ck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .recalc_rate = &omap3_dpll_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .get_parent = &omap2_init_dpll_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct clk_ops dpll_ck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .enable = &omap3_noncore_dpll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .disable = &omap3_noncore_dpll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .recalc_rate = &omap3_dpll_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .round_rate = &omap2_dpll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .set_rate = &omap3_noncore_dpll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .set_parent = &omap3_noncore_dpll_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .determine_rate = &omap3_noncore_dpll_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .get_parent = &omap2_init_dpll_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .save_context = &omap3_noncore_dpll_save_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .restore_context = &omap3_noncore_dpll_restore_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const struct clk_ops dpll_no_gate_ck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .recalc_rate = &omap3_dpll_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .get_parent = &omap2_init_dpll_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .round_rate = &omap2_dpll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .set_rate = &omap3_noncore_dpll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .set_parent = &omap3_noncore_dpll_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .determine_rate = &omap3_noncore_dpll_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .save_context = &omap3_noncore_dpll_save_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .restore_context = &omap3_noncore_dpll_restore_context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct clk_ops dpll_core_ck_ops = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const struct clk_ops dpll_ck_ops = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct clk_ops dpll_no_gate_ck_ops = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #ifdef CONFIG_ARCH_OMAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const struct clk_ops omap2_dpll_core_ck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .get_parent = &omap2_init_dpll_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .recalc_rate = &omap2_dpllcore_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .round_rate = &omap2_dpll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .set_rate = &omap2_reprogram_dpllcore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const struct clk_ops omap2_dpll_core_ck_ops = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #ifdef CONFIG_ARCH_OMAP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct clk_ops omap3_dpll_core_ck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .get_parent = &omap2_init_dpll_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .recalc_rate = &omap3_dpll_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .round_rate = &omap2_dpll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct clk_ops omap3_dpll_core_ck_ops = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #ifdef CONFIG_ARCH_OMAP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct clk_ops omap3_dpll_ck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .enable = &omap3_noncore_dpll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .disable = &omap3_noncore_dpll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .get_parent = &omap2_init_dpll_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .recalc_rate = &omap3_dpll_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .set_rate = &omap3_noncore_dpll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .set_parent = &omap3_noncore_dpll_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .determine_rate = &omap3_noncore_dpll_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .round_rate = &omap2_dpll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct clk_ops omap3_dpll5_ck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .enable = &omap3_noncore_dpll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .disable = &omap3_noncore_dpll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .get_parent = &omap2_init_dpll_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .recalc_rate = &omap3_dpll_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .set_rate = &omap3_dpll5_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .set_parent = &omap3_noncore_dpll_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .determine_rate = &omap3_noncore_dpll_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .round_rate = &omap2_dpll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const struct clk_ops omap3_dpll_per_ck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .enable = &omap3_noncore_dpll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .disable = &omap3_noncore_dpll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .get_parent = &omap2_init_dpll_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .recalc_rate = &omap3_dpll_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .set_rate = &omap3_dpll4_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .set_parent = &omap3_noncore_dpll_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .determine_rate = &omap3_noncore_dpll_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .round_rate = &omap2_dpll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct clk_ops dpll_x2_ck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .recalc_rate = &omap3_clkoutx2_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * _register_dpll - low level registration of a DPLL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @hw: hardware clock definition for the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @node: device node for the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Finalizes DPLL registration process. In case a failure (clk-ref or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * clk-bypass is missing), the clock is added to retry list and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * the initialization is retried on later stage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void __init _register_dpll(void *user,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct clk_hw *hw = user;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct dpll_data *dd = clk_hw->dpll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const struct clk_init_data *init = hw->init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) clk = of_clk_get(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pr_debug("clk-ref missing for %pOFn, retry later\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!ti_clk_retry_init(node, hw, _register_dpll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dd->clk_ref = __clk_get_hw(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) clk = of_clk_get(node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pr_debug("clk-bypass missing for %pOFn, retry later\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (!ti_clk_retry_init(node, hw, _register_dpll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dd->clk_bypass = __clk_get_hw(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* register the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) kfree(init->parent_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) kfree(init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) kfree(clk_hw->dpll_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) kfree(init->parent_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) kfree(init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) kfree(clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) defined(CONFIG_SOC_AM43XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * _register_dpll_x2 - Registers a DPLLx2 clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @node: device node for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @ops: clk_ops for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @hw_ops: clk_hw_ops for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * Initializes a DPLL x 2 clock from device tree data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void _register_dpll_x2(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) const struct clk_ops *ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) const struct clk_hw_omap_ops *hw_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct clk_init_data init = { NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct clk_hw_omap *clk_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) const char *name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) parent_name = of_clk_get_parent_name(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (!parent_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) pr_err("%pOFn must have parent\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!clk_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) clk_hw->ops = hw_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) clk_hw->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) init.ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) defined(CONFIG_SOC_DRA7XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (hw_ops == &clkhwops_omap4_dpllmx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Check if register defined, if not, drop hw-ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = of_property_count_elems_of_size(node, "reg", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ret <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) clk_hw->ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) kfree(clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* register the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) kfree(clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * @node: device node containing the DPLL info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * @ops: ops for the DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * @ddt: DPLL data template to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * Initializes a DPLL clock from device tree data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void __init of_ti_dpll_setup(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) const struct clk_ops *ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) const struct dpll_data *ddt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct clk_hw_omap *clk_hw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct clk_init_data *init = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) const char **parent_names = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct dpll_data *dd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u8 dpll_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dd = kmemdup(ddt, sizeof(*dd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) init = kzalloc(sizeof(*init), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!dd || !clk_hw || !init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) clk_hw->dpll_data = dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) clk_hw->ops = &clkhwops_omap3_dpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) clk_hw->hw.init = init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) init->name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) init->ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) init->num_parents = of_clk_get_parent_count(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!init->num_parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pr_err("%pOFn must have parent(s)\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (!parent_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) of_clk_parent_fill(node, parent_names, init->num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) init->parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * Special case for OMAP2 DPLL, register order is different due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * missing idlest_reg, also clkhwops is different. Detected from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * missing idlest_mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!dd->idlest_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #ifdef CONFIG_ARCH_OMAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) clk_hw->ops = &clkhwops_omap2xxx_dpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (dd->autoidle_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (of_property_read_bool(node, "ti,low-power-stop"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (of_property_read_bool(node, "ti,low-power-bypass"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (of_property_read_bool(node, "ti,lock"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dpll_mode |= 1 << DPLL_LOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (dpll_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dd->modes = dpll_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) _register_dpll(&clk_hw->hw, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) kfree(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) kfree(parent_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) kfree(init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) kfree(clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) defined(CONFIG_SOC_DRA7XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) of_ti_omap4_dpll_x2_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) _register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) of_ti_am3_dpll_x2_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #ifdef CONFIG_ARCH_OMAP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static void __init of_ti_omap3_dpll_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) const struct dpll_data dd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .idlest_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .enable_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .autoidle_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .mult_mask = 0x7ff << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .div1_mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .max_multiplier = 2047,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .max_divider = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .min_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .freqsel_mask = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if ((of_machine_is_compatible("ti,omap3630") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) of_machine_is_compatible("ti,omap36xx")) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) of_node_name_eq(node, "dpll5_ck"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) of_ti_dpll_setup(node, &omap3_dpll5_ck_ops, &dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) of_ti_omap3_dpll_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) const struct dpll_data dd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .idlest_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .enable_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .autoidle_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .mult_mask = 0x7ff << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .div1_mask = 0x7f << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .max_multiplier = 2047,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .max_divider = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .min_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .freqsel_mask = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) of_ti_omap3_core_dpll_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) const struct dpll_data dd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .idlest_mask = 0x1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .enable_mask = 0x7 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .autoidle_mask = 0x7 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .mult_mask = 0x7ff << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .div1_mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .max_multiplier = 2047,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .max_divider = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .min_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .freqsel_mask = 0xf00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) of_ti_omap3_per_dpll_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) const struct dpll_data dd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .idlest_mask = 0x1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .enable_mask = 0x7 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .autoidle_mask = 0x7 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .mult_mask = 0xfff << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .div1_mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .max_multiplier = 4095,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .max_divider = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .min_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .sddiv_mask = 0xff << 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .dco_mask = 0xe << 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .flags = DPLL_J_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) of_ti_omap3_per_jtype_dpll_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static void __init of_ti_omap4_dpll_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) const struct dpll_data dd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .idlest_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .enable_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .autoidle_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .mult_mask = 0x7ff << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .div1_mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .max_multiplier = 2047,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .max_divider = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .min_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) of_ti_omap4_dpll_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) const struct dpll_data dd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .idlest_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .enable_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .autoidle_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .mult_mask = 0x7ff << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .div1_mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .max_multiplier = 2047,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .max_divider = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .dcc_mask = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .min_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) of_ti_omap5_mpu_dpll_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) const struct dpll_data dd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .idlest_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .enable_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .autoidle_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .mult_mask = 0x7ff << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .div1_mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .max_multiplier = 2047,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .max_divider = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .min_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) of_ti_omap4_core_dpll_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) defined(CONFIG_SOC_DRA7XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) const struct dpll_data dd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .idlest_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .enable_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .autoidle_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .mult_mask = 0x7ff << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .div1_mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .max_multiplier = 2047,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .max_divider = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .min_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .m4xen_mask = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .lpmode_mask = 1 << 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) of_ti_omap4_m4xen_dpll_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) const struct dpll_data dd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .idlest_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .enable_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .autoidle_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .mult_mask = 0xfff << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .div1_mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .max_multiplier = 4095,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .max_divider = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .min_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .sddiv_mask = 0xff << 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .flags = DPLL_J_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) of_ti_omap4_jtype_dpll_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) const struct dpll_data dd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .idlest_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .enable_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .mult_mask = 0x7ff << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .div1_mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .max_multiplier = 2047,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .max_divider = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .min_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .max_rate = 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) of_ti_am3_no_gate_dpll_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) const struct dpll_data dd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .idlest_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .enable_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .mult_mask = 0x7ff << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .div1_mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .max_multiplier = 4095,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .max_divider = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .min_divider = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .flags = DPLL_J_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .max_rate = 2000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) of_ti_am3_jtype_dpll_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) const struct dpll_data dd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .idlest_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .enable_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .mult_mask = 0x7ff << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .div1_mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .max_multiplier = 2047,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .max_divider = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .min_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .max_rate = 2000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .flags = DPLL_J_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) "ti,am3-dpll-no-gate-j-type-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) of_ti_am3_no_gate_jtype_dpll_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static void __init of_ti_am3_dpll_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) const struct dpll_data dd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .idlest_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .enable_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .mult_mask = 0x7ff << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .div1_mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .max_multiplier = 2047,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .max_divider = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .min_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .max_rate = 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) const struct dpll_data dd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .idlest_mask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .enable_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .mult_mask = 0x7ff << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .div1_mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .max_multiplier = 2047,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .max_divider = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .min_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .max_rate = 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) of_ti_am3_core_dpll_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) const struct dpll_data dd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .enable_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .mult_mask = 0x3ff << 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .div1_mask = 0xf << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .max_divider = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .min_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) of_ti_omap2_core_dpll_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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