^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * TI composite clock support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Tero Kristo <t-kristo@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #undef pr_fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define pr_fmt(fmt) "%s: " fmt, __func__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static unsigned long ti_composite_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return ti_clk_divider_ops.recalc_rate(hw, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static long ti_composite_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int ti_composite_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const struct clk_ops ti_composite_divider_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .recalc_rate = &ti_composite_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .round_rate = &ti_composite_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .set_rate = &ti_composite_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const struct clk_ops ti_composite_gate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .enable = &omap2_dflt_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .disable = &omap2_dflt_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .is_enabled = &omap2_dflt_clk_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct component_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) const char **parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct list_head link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const char * const component_clk_types[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "gate", "divider", "mux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static LIST_HEAD(component_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static struct device_node *_get_component_node(struct device_node *node, int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct of_phandle_args clkspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) rc = of_parse_phandle_with_args(node, "clocks", "#clock-cells", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) &clkspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return clkspec.np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct component_clk *_lookup_component(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct component_clk *comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) list_for_each_entry(comp, &component_clks, link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (comp->node == node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct clk_hw_omap_comp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct device_node *comp_nodes[CLK_COMPONENT_TYPE_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct component_clk *comp_clks[CLK_COMPONENT_TYPE_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (!clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (!clk->comp_clks[idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return clk->comp_clks[idx]->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void __init _register_composite(void *user,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct clk_hw *hw = user;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct component_clk *comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const char **parent_names = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Check for presence of each component clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (!cclk->comp_nodes[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) comp = _lookup_component(cclk->comp_nodes[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (!comp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) pr_debug("component %s not ready for %pOFn, retry\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) cclk->comp_nodes[i]->name, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!ti_clk_retry_init(node, hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) _register_composite))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (cclk->comp_clks[comp->type] != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pr_err("duplicate component types for %pOFn (%s)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) node, component_clk_types[comp->type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) cclk->comp_clks[comp->type] = comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Mark this node as found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) cclk->comp_nodes[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* All components exists, proceed with registration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) for (i = CLK_COMPONENT_TYPE_MAX - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) comp = cclk->comp_clks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (!comp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (comp->num_parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) num_parents = comp->num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) parent_names = comp->parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (!num_parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pr_err("%s: no parents found for %pOFn!\n", __func__, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) clk = clk_register_composite(NULL, node->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) parent_names, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) _get_hw(cclk, CLK_COMPONENT_TYPE_MUX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) &ti_clk_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) _get_hw(cclk, CLK_COMPONENT_TYPE_DIVIDER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) &ti_composite_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) _get_hw(cclk, CLK_COMPONENT_TYPE_GATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) &ti_composite_gate_ops, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = ti_clk_add_alias(NULL, clk, node->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) clk_unregister(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Free component clock list entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!cclk->comp_clks[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) list_del(&cclk->comp_clks[i]->link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) kfree(cclk->comp_clks[i]->parent_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) kfree(cclk->comp_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) kfree(cclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void __init of_ti_composite_clk_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct clk_hw_omap_comp *cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Number of component clocks to be put inside this clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) num_clks = of_clk_get_parent_count(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (!num_clks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pr_err("composite clk %pOFn must have component(s)\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) cclk = kzalloc(sizeof(*cclk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!cclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Get device node pointers for each component clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) for (i = 0; i < num_clks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) cclk->comp_nodes[i] = _get_component_node(node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) _register_composite(&cclk->hw, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) CLK_OF_DECLARE(ti_composite_clock, "ti,composite-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) of_ti_composite_clk_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * ti_clk_add_component - add a component clock to the pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @node: device node of the component clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @hw: hardware clock definition for the component clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @type: type of the component clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * Adds a component clock to the list of available components, so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * it can be registered by a composite clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int __init ti_clk_add_component(struct device_node *node, struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) const char **parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct component_clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) num_parents = of_clk_get_parent_count(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!num_parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pr_err("component-clock %pOFn must have parent(s)\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!parent_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) of_clk_parent_fill(node, parent_names, num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) clk = kzalloc(sizeof(*clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (!clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) kfree(parent_names);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) clk->num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) clk->parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) clk->hw = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) clk->node = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) clk->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) list_add(&clk->link, &component_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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