Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * TI Clock driver internal definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2014 Texas Instruments, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *     Tero Kristo (t-kristo@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #ifndef __DRIVERS_CLK_TI_CLOCK__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define __DRIVERS_CLK_TI_CLOCK__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) struct clk_omap_divider {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	struct clk_hw		hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	struct clk_omap_reg	reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	u8			shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	u8			flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	s8			latch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u16			min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	u16			max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u16			mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	const struct clk_div_table	*table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u32		context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) struct clk_omap_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct clk_hw		hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct clk_omap_reg	reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u32			*table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u32			mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u8			shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	s8			latch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u8			flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u8			saved_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	TI_CLK_FIXED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	TI_CLK_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	TI_CLK_DIVIDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	TI_CLK_COMPOSITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	TI_CLK_FIXED_FACTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	TI_CLK_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	TI_CLK_DPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /* Global flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CLKF_INDEX_POWER_OF_TWO		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CLKF_INDEX_STARTS_AT_ONE	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CLKF_SET_RATE_PARENT		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CLKF_OMAP3			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CLKF_AM35XX			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* Gate flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CLKF_SET_BIT_TO_DISABLE		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CLKF_INTERFACE			(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CLKF_SSI			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CLKF_DSS			(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CLKF_HSOTGUSB			(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CLKF_WAIT			(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CLKF_NO_WAIT			(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CLKF_HSDIV			(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CLKF_CLKDM			(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* DPLL flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CLKF_LOW_POWER_STOP		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CLKF_LOCK			(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CLKF_LOW_POWER_BYPASS		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CLKF_PER			(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CLKF_CORE			(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CLKF_J_TYPE			(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /* CLKCTRL flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CLKF_SW_SUP			BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CLKF_HW_SUP			BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CLKF_NO_IDLEST			BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CLKF_SOC_MASK			GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CLKF_SOC_NONSEC			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CLKF_SOC_DRA72			BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CLKF_SOC_DRA74			BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CLKF_SOC_DRA76			BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CLK(dev, con, ck)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	{				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.lk = {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			.dev_id = dev,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			.con_id = con,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		},			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.clk = ck,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct ti_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	const char *clkdm_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct ti_clk *patch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct ti_clk_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	u8 bit_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u8 module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	const char * const *parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct ti_clk_divider {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u8 bit_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u16 max_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u8 module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	int *dividers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int num_dividers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct ti_clk_gate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	u8 bit_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	u8 module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Composite clock component types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	CLK_COMPONENT_TYPE_GATE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	CLK_COMPONENT_TYPE_DIVIDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	CLK_COMPONENT_TYPE_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	CLK_COMPONENT_TYPE_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  * struct ti_dt_clk - OMAP DT clock alias declarations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  * @lk: clock lookup definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  * @node_name: clock DT node to map to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct ti_dt_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct clk_lookup		lk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	char				*node_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DT_CLK(dev, con, name)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	{				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		.lk = {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			.dev_id = dev,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			.con_id = con,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		},			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		.node_name = name,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* CLKCTRL type definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct omap_clkctrl_div_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	const int *dividers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	int max_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct omap_clkctrl_bit_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	const char * const *parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	const void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct omap_clkctrl_reg_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u16 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	const struct omap_clkctrl_bit_data *bit_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	const char *clkdm_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct omap_clkctrl_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	const struct omap_clkctrl_reg_data *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) extern const struct omap_clkctrl_data omap4_clkctrl_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) extern const struct omap_clkctrl_data omap5_clkctrl_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) extern const struct omap_clkctrl_data dra7_clkctrl_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) extern const struct omap_clkctrl_data dra7_clkctrl_compat_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) extern struct ti_dt_clk dra7xx_compat_clks[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) extern const struct omap_clkctrl_data am3_clkctrl_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) extern const struct omap_clkctrl_data am3_clkctrl_compat_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) extern struct ti_dt_clk am33xx_compat_clks[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) extern const struct omap_clkctrl_data am4_clkctrl_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) extern const struct omap_clkctrl_data am4_clkctrl_compat_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) extern struct ti_dt_clk am43xx_compat_clks[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) extern const struct omap_clkctrl_data am438x_clkctrl_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) extern const struct omap_clkctrl_data am438x_clkctrl_compat_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) extern const struct omap_clkctrl_data dm814_clkctrl_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) extern const struct omap_clkctrl_data dm816_clkctrl_data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			    const char *con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 				    const char *con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) void ti_clk_add_aliases(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) void ti_clk_latch(struct clk_omap_reg *reg, s8 shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			      u8 flags, struct clk_omap_divider *div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int ti_clk_get_reg_addr(struct device_node *node, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			struct clk_omap_reg *reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) void ti_dt_clocks_register(struct ti_dt_clk *oclks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int ti_clk_retry_init(struct device_node *node, void *user,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		      ti_of_clk_init_cb_t func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int of_ti_clk_autoidle_setup(struct device_node *node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) extern const struct clk_hw_omap_ops clkhwops_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) extern const struct clk_hw_omap_ops clkhwops_iclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) extern const struct clk_ops ti_clk_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) extern const struct clk_ops ti_clk_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) extern const struct clk_ops omap_gate_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) extern struct ti_clk_features ti_clk_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int omap2_init_clk_clkdm(struct clk_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int omap2_clkops_enable_clkdm(struct clk_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) void omap2_clkops_disable_clkdm(struct clk_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int omap2_dflt_clk_enable(struct clk_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) void omap2_dflt_clk_disable(struct clk_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				   struct clk_omap_reg *other_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 				   u8 *other_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 				struct clk_omap_reg *idlest_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 				u8 *idlest_bit, u8 *idlest_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u8 omap2_init_dpll_parent(struct clk_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int omap3_noncore_dpll_enable(struct clk_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) void omap3_noncore_dpll_disable(struct clk_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 				unsigned long parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 					   unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 					   unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 					   u8 index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 				      struct clk_rate_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			   unsigned long *parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 				    unsigned long parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)  * OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)  * that are sourced by DPLL5, and both of these require this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)  * to be at 120 MHz for proper operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define OMAP3_DPLL5_FREQ_FOR_USBHOST	120000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			 unsigned long parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 				    unsigned long parent_rate, u8 index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			 unsigned long parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) void omap3_clk_lock_dpll5(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 					 unsigned long parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 				    unsigned long target_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 				    unsigned long *parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 				       struct clk_rate_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int omap2_clk_for_each(int (*fn)(struct clk_hw_omap *hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) extern struct ti_clk_ll_ops *ti_clk_ll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #endif