^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP2/3/4 DPLL clock functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2008 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004-2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Contacts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Richard Woodruff <r-woodruff2@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* DPLL rate rounding: minimum DPLL multiplier, divider values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DPLL_MIN_MULTIPLIER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DPLL_MIN_DIVIDER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Possible error results from _dpll_test_mult */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DPLL_MULT_UNDERFLOW -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Scale factor to mitigate roundoff errors in DPLL rate rounding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * The higher the scale factor, the greater the risk of arithmetic overflow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * must be a power of DPLL_SCALE_BASE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DPLL_SCALE_FACTOR 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DPLL_SCALE_BASE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * From device data manual section 4.3 "DPLL and DLL Specifications".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* _dpll_test_fint() return codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DPLL_FINT_UNDERFLOW -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DPLL_FINT_INVALID -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Private functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * _dpll_test_fint - test whether an Fint value is valid for the DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @clk: DPLL struct clk to test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @n: divider value (N) to test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Tests whether a particular divider @n will result in a valid DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * (assuming that it is counting N upwards), or -2 if the enclosing loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * should skip to the next iteration (again assuming N is increasing).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct dpll_data *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) long fint, fint_min, fint_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) dd = clk->dpll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* DPLL divider must result in a valid jitter correction val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) fint = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)) / n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (dd->flags & DPLL_J_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) fint_min = ti_clk_get_features()->fint_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) fint_max = ti_clk_get_features()->fint_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!fint_min || !fint_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) WARN(1, "No fint limits available!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return DPLL_FINT_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (fint < ti_clk_get_features()->fint_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dd->max_divider = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ret = DPLL_FINT_UNDERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) } else if (fint > ti_clk_get_features()->fint_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dd->min_divider = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = DPLL_FINT_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) } else if (fint > ti_clk_get_features()->fint_band1_max &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) fint < ti_clk_get_features()->fint_band2_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pr_debug("rejecting n=%d due to Fint failure\n", n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ret = DPLL_FINT_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int m, unsigned int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned long long num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) num = (unsigned long long)parent_rate * m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) do_div(num, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * _dpll_test_mult - test a DPLL multiplier value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @m: pointer to the DPLL m (multiplier) value under test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @n: current DPLL n (divider) value under test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @new_rate: pointer to storage for the resulting rounded rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @target_rate: the desired DPLL rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @parent_rate: the DPLL's parent clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * This code tests a DPLL multiplier value, ensuring that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * resulting rate will not be higher than the target_rate, and that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * the multiplier value itself is valid for the DPLL. Initially, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * integer pointed to by the m argument should be prescaled by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * a non-scaled m upon return. This non-scaled m will result in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * new_rate as close as possible to target_rate (but not greater than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * target_rate) given the current (parent_rate, n, prescaled m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * non-scaled m attempted to underflow, which can allow the calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * function to bail out early; or 0 upon success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned long target_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int r = 0, carry = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Unscale m and round if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) carry = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *m = (*m / DPLL_SCALE_FACTOR) + carry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * The new rate must be <= the target rate to avoid programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * a rate that is impossible for the hardware to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (*new_rate > target_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) (*m)--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) *new_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Guard against m underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (*m < DPLL_MIN_MULTIPLIER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) *m = DPLL_MIN_MULTIPLIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *new_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) r = DPLL_MULT_UNDERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (*new_rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @v: bitfield value of the DPLL enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Checks given DPLL enable bitfield to see whether the DPLL is in bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int _omap2_dpll_is_in_bypass(u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u8 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mask = ti_clk_get_features()->dpll_bypass_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Each set bit in the mask corresponds to a bypass value equal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * to the bitshift. Go through each set-bit in the mask and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * compare against the given register value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) while (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) val = __ffs(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mask ^= (1 << val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (v == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Public functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 omap2_init_dpll_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct clk_hw_omap *clk = to_clk_hw_omap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct dpll_data *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dd = clk->dpll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) v &= dd->enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) v >>= __ffs(dd->enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Reparent the struct clk in case the dpll is in bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (_omap2_dpll_is_in_bypass(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @clk: struct clk * of a DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * DPLLs can be locked or bypassed - basically, enabled or disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * When locked, the DPLL output depends on the M and N values. When
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * if the clock @clk is not a DPLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u64 dpll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 dpll_mult, dpll_div, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct dpll_data *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dd = clk->dpll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (!dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Return bypass rate if DPLL is bypassed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) v &= dd->enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) v >>= __ffs(dd->enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (_omap2_dpll_is_in_bypass(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return clk_hw_get_rate(dd->clk_bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dpll_mult = v & dd->mult_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dpll_mult >>= __ffs(dd->mult_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dpll_div = v & dd->div1_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dpll_div >>= __ffs(dd->div1_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dpll_clk = (u64)clk_hw_get_rate(dd->clk_ref) * dpll_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) do_div(dpll_clk, dpll_div + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return dpll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* DPLL rate rounding code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * @clk: struct clk * for a DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * @target_rate: desired DPLL clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * Given a DPLL and a desired target rate, round the target rate to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * possible, programmable rate for this DPLL. Attempts to select the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * minimum possible n. Stores the computed (m, n) in the DPLL's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * dpll_data structure so set_rate() will not need to call this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * (expensive) function again. Returns ~0 if the target rate cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * be rounded, or the rounded rate upon success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct clk_hw_omap *clk = to_clk_hw_omap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int m, n, r, scaled_max_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int min_delta_m = INT_MAX, min_delta_n = INT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned long scaled_rt_rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned long new_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct dpll_data *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned long ref_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) long delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) long prev_min_delta = LONG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) const char *clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (!clk || !clk->dpll_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dd = clk->dpll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (dd->max_rate && target_rate > dd->max_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) target_rate = dd->max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ref_rate = clk_hw_get_rate(dd->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) clk_name = clk_hw_get_name(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) clk_name, target_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dd->last_rounded_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) for (n = dd->min_divider; n <= dd->max_divider; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Is the (input clk, divider) pair valid for the DPLL? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) r = _dpll_test_fint(clk, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (r == DPLL_FINT_UNDERFLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) else if (r == DPLL_FINT_INVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Compute the scaled DPLL multiplier, based on the divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) m = scaled_rt_rp * n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * Since we're counting n up, a m overflow means we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * can bail out completely (since as n increases in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * the next iteration, there's no way that m can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * increase beyond the current m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (m > scaled_max_m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) r = _dpll_test_mult(&m, n, &new_rate, target_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ref_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* m can't be set low enough for this n - try with a larger n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (r == DPLL_MULT_UNDERFLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* skip rates above our target rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) delta = target_rate - new_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (delta < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (delta < prev_min_delta) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) prev_min_delta = delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) min_delta_m = m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) min_delta_n = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) clk_name, m, n, new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (delta == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (prev_min_delta == LONG_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pr_debug("clock: %s: cannot round to rate %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) clk_name, target_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dd->last_rounded_m = min_delta_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dd->last_rounded_n = min_delta_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dd->last_rounded_rate = target_rate - prev_min_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return dd->last_rounded_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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