^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Default clock type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2005-2008, 2015 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004-2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Contacts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Richard Woodruff <r-woodruff2@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Tero Kristo <t-kristo@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * for a module to indicate that it is no longer in idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MAX_MODULE_ENABLE_WAIT 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * CM module register offsets, used for calculating the companion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * register addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CM_FCLKEN 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CM_ICLKEN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * _wait_idlest_generic - wait for a module to leave the idle state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @clk: module clock to wait for (needed for register offsets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @reg: virtual address of module IDLEST register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @mask: value to mask against to determine if the module is active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @idlest: idle state indicator (0 or 1) for the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @name: name of the clock (for printk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Wait for a module to leave idle, where its idle-status register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * not inside the CM module. Returns 1 if the module left idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * promptly, or 0 if the module did not leave idle before the timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * elapsed. XXX Deprecated - should be moved into drivers for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * individual IP block that the IDLEST register exists in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int _wait_idlest_generic(struct clk_hw_omap *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct clk_omap_reg *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 mask, u8 idlest, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int i = 0, ena = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ena = (idlest) ? 0 : mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Wait until module enters enabled state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) for (i = 0; i < MAX_MODULE_ENABLE_WAIT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if ((ti_clk_ll_ops->clk_readl(reg) & mask) == ena)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (i < MAX_MODULE_ENABLE_WAIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pr_debug("omap clock: module associated with clock %s ready after %d loops\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) name, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) name, MAX_MODULE_ENABLE_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @clk: struct clk * belonging to the module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * If the necessary clocks for the OMAP hardware IP block that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * corresponds to clock @clk are enabled, then wait for the module to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * indicate readiness (i.e., to leave IDLE). This code does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * belong in the clock code and will be moved in the medium term to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * module-dependent code. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct clk_omap_reg companion_reg, idlest_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 other_bit, idlest_bit, idlest_val, idlest_reg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) s16 prcm_mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Not all modules have multiple clocks that their IDLEST depends on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (clk->ops->find_companion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) clk->ops->find_companion(clk, &companion_reg, &other_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!(ti_clk_ll_ops->clk_readl(&companion_reg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) (1 << other_bit)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) r = ti_clk_ll_ops->cm_split_idlest_reg(&idlest_reg, &prcm_mod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) &idlest_reg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* IDLEST register not in the CM module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) _wait_idlest_generic(clk, &idlest_reg, (1 << idlest_bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) idlest_val, clk_hw_get_name(&clk->hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ti_clk_ll_ops->cm_wait_module_ready(0, prcm_mod, idlest_reg_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) idlest_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * omap2_clk_dflt_find_companion - find companion clock to @clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @clk: struct clk * to find the companion clock of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @other_bit: u8 ** to return the companion clock bit shift in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Note: We don't need special code here for INVERT_ENABLE for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * time being since INVERT_ENABLE only applies to clocks enabled by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * CM_CLKEN_PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * just a matter of XORing the bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Some clocks don't have companion clocks. For example, modules with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * only an interface clock (such as MAILBOXES) don't have a companion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * clock. Right now, this code relies on the hardware exporting a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * in the correct companion register that indicates that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * nonexistent 'companion clock' is active. Future patches will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * associate this type of code with per-module data structures to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * avoid this issue, and remove the casts. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk_omap_reg *other_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 *other_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) memcpy(other_reg, &clk->enable_reg, sizeof(*other_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * it's just a matter of XORing the bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) other_reg->offset ^= (CM_FCLKEN ^ CM_ICLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *other_bit = clk->enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @clk: struct clk * to find IDLEST info for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @idlest_reg: void __iomem ** to return the CM_IDLEST va in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @idlest_bit: u8 * to return the CM_IDLEST bit shift in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @idlest_val: u8 * to return the idle status indicator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Return the CM_IDLEST register address and bit shift corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * to the module that "owns" this clock. This default code assumes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * the IDLEST register address ID corresponds to the CM_*CLKEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * register address ID (e.g., that CM_FCLKEN2 corresponds to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * CM_IDLEST2). This is not true for all modules. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct clk_omap_reg *idlest_reg, u8 *idlest_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u8 *idlest_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) idlest_reg->offset &= ~0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) idlest_reg->offset |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *idlest_bit = clk->enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * 34xx reverses this, just to keep us on our toes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * AM35xx uses both, depending on the module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *idlest_val = ti_clk_get_features()->cm_idlest_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * omap2_dflt_clk_enable - enable a clock in the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @hw: struct clk_hw * of the clock to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * Enable the clock @hw in the hardware. We first call into the OMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * clockdomain code to "enable" the corresponding clockdomain if this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * is the first enabled user of the clockdomain. Then program the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * hardware to enable the clock. Then wait for the IP block that uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * this clock to leave idle (if applicable). Returns the error value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * from clkdm_clk_enable() if it terminated with an error, or -EINVAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * if @hw has a null clock enable_reg, or zero upon success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int omap2_dflt_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct clk_hw_omap *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) bool clkdm_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clkdm_control = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) clkdm_control = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) clk = to_clk_hw_omap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (clkdm_control && clk->clkdm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) WARN(1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "%s: could not enable %s's clockdomain %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) __func__, clk_hw_get_name(hw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) clk->clkdm_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* FIXME should not have INVERT_ENABLE bit here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) v = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (clk->flags & INVERT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) v &= ~(1 << clk->enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) v |= (1 << clk->enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ti_clk_ll_ops->clk_writel(v, &clk->enable_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); /* OCP barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (clk->ops && clk->ops->find_idlest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) _omap2_module_wait_ready(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * omap2_dflt_clk_disable - disable a clock in the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @hw: struct clk_hw * of the clock to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * Disable the clock @hw in the hardware, and call into the OMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * clockdomain code to "disable" the corresponding clockdomain if all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * clocks/hwmods in that clockdomain are now disabled. No return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) void omap2_dflt_clk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct clk_hw_omap *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) clk = to_clk_hw_omap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) v = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (clk->flags & INVERT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) v |= (1 << clk->enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) v &= ~(1 << clk->enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ti_clk_ll_ops->clk_writel(v, &clk->enable_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* No OCP barrier needed here since it is a disable operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (!(ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) clk->clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * omap2_dflt_clk_is_enabled - is clock enabled in the hardware?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * @hw: struct clk_hw * to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * Return 1 if the clock represented by @hw is enabled in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * hardware, or 0 otherwise. Intended for use in the struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * clk_ops.is_enabled function pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int omap2_dflt_clk_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct clk_hw_omap *clk = to_clk_hw_omap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) v = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (clk->flags & INVERT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) v ^= BIT(clk->enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) v &= BIT(clk->enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return v ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) const struct clk_hw_omap_ops clkhwops_wait = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .find_idlest = omap2_clk_dflt_find_idlest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .find_companion = omap2_clk_dflt_find_companion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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