^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * TI clock support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Tero Kristo <t-kristo@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #undef pr_fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define pr_fmt(fmt) "%s: " fmt, __func__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static LIST_HEAD(clk_hw_omap_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct ti_clk_ll_ops *ti_clk_ll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static struct device_node *clocks_node_ptr[CLK_MAX_MEMMAPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct ti_clk_features ti_clk_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct clk_iomap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void __iomem *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void clk_memmap_writel(u32 val, const struct clk_omap_reg *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct clk_iomap *io = clk_memmaps[reg->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (reg->ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) writel_relaxed(val, reg->ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) else if (io->regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) regmap_write(io->regmap, reg->offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) writel_relaxed(val, io->mem + reg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void _clk_rmw(u32 val, u32 mask, void __iomem *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) v = readl_relaxed(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) v &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) v |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) writel_relaxed(v, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static void clk_memmap_rmw(u32 val, u32 mask, const struct clk_omap_reg *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct clk_iomap *io = clk_memmaps[reg->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (reg->ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) _clk_rmw(val, mask, reg->ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) } else if (io->regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) regmap_update_bits(io->regmap, reg->offset, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) _clk_rmw(val, mask, io->mem + reg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static u32 clk_memmap_readl(const struct clk_omap_reg *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct clk_iomap *io = clk_memmaps[reg->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (reg->ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) val = readl_relaxed(reg->ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) else if (io->regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) regmap_read(io->regmap, reg->offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) val = readl_relaxed(io->mem + reg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * ti_clk_setup_ll_ops - setup low level clock operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @ops: low level clock ops descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Sets up low level clock operations for TI clock driver. This is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * to provide various callbacks for the clock driver towards platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * specific code. Returns 0 on success, -EBUSY if ll_ops have been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * registered already.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (ti_clk_ll_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pr_err("Attempt to register ll_ops multiple times.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ti_clk_ll_ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ops->clk_readl = clk_memmap_readl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ops->clk_writel = clk_memmap_writel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ops->clk_rmw = clk_memmap_rmw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * ti_dt_clocks_register - register DT alias clocks during boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @oclks: list of clocks to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Register alias or non-standard DT clock entries during boot. By
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * default, DT clocks are found based on their node name. If any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * additional con-id / dev-id -> clock mapping is required, use this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * function to list these.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct ti_dt_clk *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct device_node *node, *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct of_phandle_args clkspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) char buf[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) char *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) char *tags[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int num_args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static bool clkctrl_nodes_missing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static bool has_clkctrl_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static bool compat_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) compat_mode = ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) for (c = oclks; c->node_name != NULL; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) strcpy(buf, c->node_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ptr = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) for (i = 0; i < 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) tags[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) num_args = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) while (*ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (*ptr == ':') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (num_args >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pr_warn("Bad number of tags on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) c->node_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tags[num_args++] = ptr + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) *ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (num_args && clkctrl_nodes_missing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) node = of_find_node_by_name(NULL, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (num_args && compat_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) parent = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) node = of_get_child_by_name(parent, "clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) node = of_get_child_by_name(parent, "clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) of_node_put(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) clkspec.np = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) clkspec.args_count = num_args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) for (i = 0; i < num_args; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = kstrtoint(tags[i], i ? 10 : 16, clkspec.args + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pr_warn("Bad tag in %s at %d: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) c->node_name, i, tags[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) clk = of_clk_get_from_provider(&clkspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) c->lk.clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) clkdev_add(&c->lk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (num_args && !has_clkctrl_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) np = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "ti,clkctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) has_clkctrl_data = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) clkctrl_nodes_missing = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pr_warn("missing clkctrl nodes, please update your dts.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pr_warn("failed to lookup clock node %s, ret=%ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) c->node_name, PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct clk_init_item {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) void *user;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ti_of_clk_init_cb_t func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct list_head link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static LIST_HEAD(retry_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * ti_clk_retry_init - retries a failed clock init at later phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @node: device not for the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @user: user data pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @func: init function to be called for the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * Adds a failed clock init to the retry list. The retry list is parsed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * once all the other clocks have been initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int __init ti_clk_retry_init(struct device_node *node, void *user,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ti_of_clk_init_cb_t func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct clk_init_item *retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pr_debug("%pOFn: adding to retry list...\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) retry = kzalloc(sizeof(*retry), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!retry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) retry->node = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) retry->func = func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) retry->user = user;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) list_add(&retry->link, &retry_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * ti_clk_get_reg_addr - get register address for a clock register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * @node: device node for the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @index: register index from the clock node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @reg: pointer to target register struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Builds clock register address from device tree information, and returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * the data via the provided output pointer @reg. Returns 0 on success,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * negative error value on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int ti_clk_get_reg_addr(struct device_node *node, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct clk_omap_reg *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) for (i = 0; i < CLK_MAX_MEMMAPS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (clocks_node_ptr[i] == node->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (i == CLK_MAX_MEMMAPS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pr_err("clk-provider not found for %pOFn!\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) reg->index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (of_property_read_u32_index(node, "reg", index, &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pr_err("%pOFn must have reg[%d]!\n", node, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) reg->offset = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) reg->ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) void ti_clk_latch(struct clk_omap_reg *reg, s8 shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 latch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (shift < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) latch = 1 << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ti_clk_ll_ops->clk_rmw(latch, latch, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ti_clk_ll_ops->clk_rmw(0, latch, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ti_clk_ll_ops->clk_readl(reg); /* OCP barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * omap2_clk_provider_init - init master clock provider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * @parent: master node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * @index: internal index for clk_reg_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * @syscon: syscon regmap pointer for accessing clock registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * @mem: iomem pointer for the clock provider memory area, only used if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * syscon is not provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Initializes a master clock IP block. This basically sets up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * mapping from clocks node to the memory map index. All the clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * are then initialized through the common of_clk_init call, and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * clocks will access their memory maps based on the node layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Returns 0 in success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int __init omap2_clk_provider_init(struct device_node *parent, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct regmap *syscon, void __iomem *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct device_node *clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct clk_iomap *io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* get clocks for this parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) clocks = of_get_child_by_name(parent, "clocks");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!clocks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pr_err("%pOFn missing 'clocks' child node.\n", parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* add clocks node info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) clocks_node_ptr[index] = clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) io = kzalloc(sizeof(*io), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (!io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) io->regmap = syscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) io->mem = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) clk_memmaps[index] = io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * omap2_clk_legacy_provider_init - initialize a legacy clock provider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * @index: index for the clock provider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * @mem: iomem pointer for the clock provider memory area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Initializes a legacy clock provider memory mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct clk_iomap *io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) io = memblock_alloc(sizeof(*io), SMP_CACHE_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (!io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) panic("%s: Failed to allocate %zu bytes\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) sizeof(*io));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) io->mem = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) clk_memmaps[index] = io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * ti_dt_clk_init_retry_clks - init clocks from the retry list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * Initializes any clocks that have failed to initialize before,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * reasons being missing parent node(s) during earlier init. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * typically happens only for DPLLs which need to have both of their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * parent clocks ready during init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) void ti_dt_clk_init_retry_clks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct clk_init_item *retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct clk_init_item *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int retries = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) while (!list_empty(&retry_list) && retries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) list_for_each_entry_safe(retry, tmp, &retry_list, link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) pr_debug("retry-init: %pOFn\n", retry->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) retry->func(retry->user, retry->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) list_del(&retry->link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) kfree(retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) retries--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const struct of_device_id simple_clk_match_table[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { .compatible = "fixed-clock" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { .compatible = "fixed-factor-clock" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * ti_clk_add_aliases - setup clock aliases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * Sets up any missing clock aliases. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) void __init ti_clk_add_aliases(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) for_each_matching_node(np, simple_clk_match_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct of_phandle_args clkspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) clkspec.np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) clk = of_clk_get_from_provider(&clkspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ti_clk_add_alias(NULL, clk, np->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * ti_clk_setup_features - setup clock features flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * @features: features definition to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * Initializes the clock driver features flags based on platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * provided data. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) void __init ti_clk_setup_features(struct ti_clk_features *features)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) memcpy(&ti_clk_features, features, sizeof(*features));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * ti_clk_get_features - get clock driver features flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * Get TI clock driver features description. Returns a pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * to the current feature setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) const struct ti_clk_features *ti_clk_get_features(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return &ti_clk_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * omap2_clk_enable_init_clocks - prepare & enable a list of clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * @clk_names: ptr to an array of strings of clock names to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * @num_clocks: number of clock names in @clk_names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * Prepare and enable a list of clocks, named by @clk_names. No
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * return value. XXX Deprecated; only needed until these clocks are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * properly claimed and enabled by the drivers or core code that uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * them. XXX What code disables & calls clk_put on these clocks?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct clk *init_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) for (i = 0; i < num_clocks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) init_clk = clk_get(NULL, clk_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (WARN(IS_ERR(init_clk), "could not find init clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) clk_names[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) clk_prepare_enable(init_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * ti_clk_add_alias - add a clock alias for a TI clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * @dev: device alias for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * @clk: clock handle to create alias for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * @con: connection ID for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * Creates a clock alias for a TI clock. Allocates the clock lookup entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * and assigns the data to it. Returns 0 if successful, negative error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * value otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct clk_lookup *cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) cl = kzalloc(sizeof(*cl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (!cl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) cl->dev_id = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) cl->con_id = con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) cl->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) clkdev_add(cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * ti_clk_register - register a TI clock to the common clock framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * @dev: device for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * @hw: hardware clock handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * @con: connection ID for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * Registers a TI clock to the common clock framework, and adds a clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * alias for it. Returns a handle to the registered clock if successful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * ERR_PTR value in failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) const char *con)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) clk = clk_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = ti_clk_add_alias(dev, clk, con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) clk_unregister(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * ti_clk_register_omap_hw - register a clk_hw_omap to the clock framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * @dev: device for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * @hw: hardware clock handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * @con: connection ID for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * Registers a clk_hw_omap clock to the clock framewor, adds a clock alias
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * for it, and adds the list to the available clk_hw_omap type clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * Returns a handle to the registered clock if successful, ERR_PTR value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * in failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) const char *con)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct clk_hw_omap *oclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) clk = ti_clk_register(dev, hw, con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) oclk = to_clk_hw_omap(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) list_add(&oclk->node, &clk_hw_omap_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * omap2_clk_for_each - call function for each registered clk_hw_omap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * @fn: pointer to a callback function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * Call @fn for each registered clk_hw_omap, passing @hw to each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * function. @fn must return 0 for success or any other value for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * failure. If @fn returns non-zero, the iteration across clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * will stop and the non-zero return value will be passed to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * caller of omap2_clk_for_each().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int omap2_clk_for_each(int (*fn)(struct clk_hw_omap *hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct clk_hw_omap *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) list_for_each_entry(hw, &clk_hw_omap_clocks, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ret = (*fn)(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * omap2_clk_is_hw_omap - check if the provided clk_hw is OMAP clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * @hw: clk_hw to check if it is an omap clock or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * Checks if the provided clk_hw is OMAP clock or not. Returns true if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * it is, false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) bool omap2_clk_is_hw_omap(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct clk_hw_omap *oclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) list_for_each_entry(oclk, &clk_hw_omap_clocks, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (&oclk->hw == hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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