^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/clock/dm816.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const struct omap_clkctrl_reg_data dm816_default_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) { DM816_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const struct omap_clkctrl_reg_data dm816_alwon_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { DM816_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { DM816_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { DM816_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { DM816_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { DM816_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { DM816_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { DM816_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { DM816_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { DM816_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { DM816_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { DM816_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { DM816_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { DM816_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { DM816_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { DM816_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { DM816_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { DM816_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { DM816_SPINBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { DM816_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { DM816_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { DM816_DAVINCI_MDIO_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { DM816_EMAC1_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { DM816_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { DM816_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { DM816_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { DM816_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { DM816_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { DM816_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { DM816_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const struct omap_clkctrl_data dm816_clkctrl_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { 0x48180500, dm816_default_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { 0x48181400, dm816_alwon_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct ti_dt_clk dm816x_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const char *enable_init_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "ddr_pll_clk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "ddr_pll_clk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "ddr_pll_clk3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "sysclk6_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int __init dm816x_dt_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ti_dt_clocks_register(dm816x_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) omap2_clk_disable_autoidle_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ti_clk_add_aliases();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) omap2_clk_enable_init_clocks(enable_init_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ARRAY_SIZE(enable_init_clks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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