^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <dt-bindings/clock/dm814.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) static const struct omap_clkctrl_reg_data dm814_default_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) { DM814_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "pll260dcoclkldo" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) { DM814_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) { DM814_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) { DM814_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) { DM814_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) { DM814_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { DM814_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { DM814_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { DM814_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { DM814_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { DM814_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { DM814_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { DM814_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { DM814_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { DM814_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) omap_clkctrl_reg_data dm814_alwon_ethernet_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { 0, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { 0x48180500, dm814_default_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { 0x48181400, dm814_alwon_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { 0x481815d4, dm814_alwon_ethernet_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct ti_dt_clk dm814_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static bool timer_clocks_initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int __init dm814x_adpll_early_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (!timer_clocks_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) np = of_find_node_by_name(NULL, "pllss");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pr_err("Could not find node for plls\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) of_platform_populate(np, NULL, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) core_initcall(dm814x_adpll_early_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const char * const init_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "pll040clkout", /* MPU 481c5040.adpll.clkout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "pll290clkout", /* DDR 481c5290.adpll.clkout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int __init dm814x_adpll_enable_init_clocks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (!timer_clocks_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) clock = clk_get(NULL, init_clocks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (WARN(IS_ERR(clock), "could not find init clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) init_clocks[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) err = clk_prepare_enable(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (WARN(err, "could not enable init clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) init_clocks[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) postcore_initcall(dm814x_adpll_enable_init_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int __init dm814x_dt_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ti_dt_clocks_register(dm814_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) omap2_clk_disable_autoidle_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ti_clk_add_aliases();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) omap2_clk_enable_init_clocks(NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) timer_clocks_initialized = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags