^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DRA7 Clock init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Tero Kristo (t-kristo@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/dra7.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DRA7_DPLL_GMAC_DEFFREQ 1000000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DRA7_DPLL_USB_DEFFREQ 960000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { DRA7_MPU_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) "dpll_abe_m2x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "dpll_core_h22x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP | CLKF_NO_IDLEST, "ipu1-clkctrl:0000:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "per_abe_x1_gfclk2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "video1_clk2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "video2_clk2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "hdmi_clk2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "abe_24m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "abe_sys_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "func_24m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "atl_clkin3_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "atl_clkin2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "atl_clkin1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "atl_clkin0_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "sys_clkin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "ref_clkin0_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "ref_clkin1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "ref_clkin2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "ref_clkin3_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "mlb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "mlbp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "timer_sys_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "sys_32k_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "sys_clkin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "ref_clkin0_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "ref_clkin1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "ref_clkin2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "ref_clkin3_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "abe_giclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "video1_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "video2_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "hdmi_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "clkoutmux0_clk_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "func_48m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "dpll_per_m2x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { DRA7_IPU_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { DRA7_RTC_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const char * const dra7_cam_gfclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "l3_iclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "core_iss_main_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const struct omap_clkctrl_bit_data dra7_cam_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { 24, TI_CLK_MUX, dra7_cam_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct omap_clkctrl_reg_data dra7_cam_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { DRA7_CAM_VIP1_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { DRA7_CAM_VIP2_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { DRA7_CAM_VIP3_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct omap_clkctrl_reg_data dra7_vpe_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { DRA7_VPE_VPE_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h23x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { DRA7_L3MAIN1_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { DRA7_L3MAIN1_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { DRA7_L3MAIN1_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { DRA7_L3MAIN1_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { DRA7_L3MAIN1_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { DRA7_L3MAIN1_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { DRA7_DMA_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { DRA7_EMIF_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "sys_32k_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "video1_clkin_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "video2_clkin_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "hdmi_clkin_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "l3_iclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "dpll_abe_m2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "atl-clkctrl:0000:24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { DRA7_ATL_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl-clkctrl:0000:26" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { DRA7_L4CFG_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { DRA7_L4CFG_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { DRA7_L4CFG_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { DRA7_L4CFG_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { DRA7_L4CFG_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { DRA7_L4CFG_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { DRA7_L4CFG_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { DRA7_L4CFG_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { DRA7_L4CFG_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { DRA7_L4CFG_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { DRA7_L4CFG_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { DRA7_L4CFG_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { DRA7_L4CFG_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { DRA7_L4CFG_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { DRA7_L4CFG_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { DRA7_L3INSTR_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { DRA7_L3INSTR_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const char * const dra7_dss_dss_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "dpll_per_h12x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "func_48m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "hdmi_dpll_clk_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "sys_32k_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const char * const dra7_dss_video1_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "video1_dpll_clk_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const char * const dra7_dss_video2_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "video2_dpll_clk_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { DRA7_DSS_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { DRA7_DSS_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const char * const dra7_gpu_core_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "dpll_core_h14x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "dpll_per_h14x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "dpll_gpu_m2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const char * const dra7_gpu_hyd_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "dpll_core_h14x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "dpll_per_h14x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "dpll_gpu_m2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const struct omap_clkctrl_bit_data dra7_gpu_core_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { 24, TI_CLK_MUX, dra7_gpu_core_mux_parents, NULL, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { 26, TI_CLK_MUX, dra7_gpu_hyd_mux_parents, NULL, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct omap_clkctrl_reg_data dra7_gpu_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { DRA7_GPU_CLKCTRL, dra7_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "func_128m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "dpll_per_m2x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "l3init-clkctrl:0008:24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .max_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "l3init-clkctrl:0010:24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .max_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "l3init_960m_gfclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const char * const dra7_sata_ref_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "sys_clkin1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { DRA7_L3INIT_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { DRA7_L3INIT_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "apll_pcie_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) "optfclk_pciephy_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const struct omap_clkctrl_reg_data dra7_pcie_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { DRA7_PCIE_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { DRA7_PCIE_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) "dpll_gmac_h11x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) "rmii_clk_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "video1_clkin_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) "video2_clkin_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) "dpll_abe_m2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) "hdmi_clkin_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "l3_iclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) { DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "gmac_main_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) "timer_sys_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) "sys_32k_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) "sys_clkin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) "ref_clkin0_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) "ref_clkin1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) "ref_clkin2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "ref_clkin3_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "abe_giclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "video1_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "video2_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) "hdmi_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) "l4per-clkctrl:00f8:24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .max_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) "l4per-clkctrl:0100:24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .max_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) { DRA7_L4PER_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0000:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) { DRA7_L4PER_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { DRA7_L4PER_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) { DRA7_L4PER_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) { DRA7_L4PER_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) { DRA7_L4PER_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) { DRA7_L4PER_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) { DRA7_L4PER_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) { DRA7_L4PER_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) { DRA7_L4PER_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) { DRA7_L4PER_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) { DRA7_L4PER_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) { DRA7_L4PER_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) { DRA7_L4PER_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) { DRA7_L4PER_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) { DRA7_L4PER_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) { DRA7_L4PER_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) { DRA7_L4PER_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) { DRA7_L4PER_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) { DRA7_L4PER_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) { DRA7_L4PER_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) { DRA7_L4PER_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) { DRA7_L4PER_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) { DRA7_L4PER_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) { DRA7_L4PER_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:00f8:25" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) { DRA7_L4PER_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0100:25" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) { DRA7_L4PER_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0118:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) { DRA7_L4PER_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0120:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) { DRA7_L4PER_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0128:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) { DRA7_L4PER_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0130:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) { DRA7_L4PER_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0148:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) { DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) { DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) { DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) { DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) { DRA7_L4SEC_SHAM2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) "func_128m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) "dpll_per_h13x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) "l4per2-clkctrl:012c:24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .max_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) { DRA7_L4PER2_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) { DRA7_L4PER2_PRUSS1_CLKCTRL, NULL, CLKF_SW_SUP, "" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) { DRA7_L4PER2_PRUSS2_CLKCTRL, NULL, CLKF_SW_SUP, "" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) { DRA7_L4PER2_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) { DRA7_L4PER2_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) { DRA7_L4PER2_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) { DRA7_L4PER2_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:012c:25" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) { DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) { DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) { DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:22" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) { DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) { DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) { DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) { DRA7_L4PER2_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01dc:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) { DRA7_L4PER2_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) { DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01f8:22" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) { DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01fc:22" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static const struct omap_clkctrl_reg_data dra7_l4per3_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) { DRA7_L4PER3_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) { DRA7_L4PER3_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00b4:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) { DRA7_L4PER3_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00bc:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) { DRA7_L4PER3_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00c4:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) { DRA7_L4PER3_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:011c:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) "sys_clkin1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) "sys_clkin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) { DRA7_WKUPAON_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) { DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) { DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) { DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) { DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) { DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) { DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) { DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) { DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SOC_DRA76, "mcan_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) { 0x4a005320, dra7_mpu_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) { 0x4a005420, dra7_dsp1_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) { 0x4a005520, dra7_ipu1_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) { 0x4a005550, dra7_ipu_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) { 0x4a005620, dra7_dsp2_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) { 0x4a005720, dra7_rtc_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) { 0x4a005760, dra7_vpe_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) { 0x4a008620, dra7_coreaon_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) { 0x4a008720, dra7_l3main1_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) { 0x4a008920, dra7_ipu2_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) { 0x4a008a20, dra7_dma_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) { 0x4a008b20, dra7_emif_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) { 0x4a008c00, dra7_atl_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) { 0x4a008d20, dra7_l4cfg_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) { 0x4a008e20, dra7_l3instr_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) { 0x4a009020, dra7_cam_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) { 0x4a009120, dra7_dss_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) { 0x4a009220, dra7_gpu_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) { 0x4a009320, dra7_l3init_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) { 0x4a0093b0, dra7_pcie_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) { 0x4a0093d0, dra7_gmac_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) { 0x4a009728, dra7_l4per_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) { 0x4a0098a0, dra7_l4sec_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) { 0x4a00970c, dra7_l4per2_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) { 0x4a009714, dra7_l4per3_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) { 0x4ae07820, dra7_wkupaon_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static struct ti_dt_clk dra7xx_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) DT_CLK(NULL, "atl_gfclk_mux", "atl-clkctrl:0000:26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) DT_CLK(NULL, "dss_hdmi_clk", "dss-clkctrl:0000:10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) DT_CLK(NULL, "dss_video1_clk", "dss-clkctrl:0000:12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) DT_CLK(NULL, "dss_video2_clk", "dss-clkctrl:0000:13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) DT_CLK(NULL, "gmac_rft_clk_mux", "gmac-clkctrl:0000:25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0038:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0040:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0048:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0050:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0058:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00e8:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f0:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu-clkctrl:0000:28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu-clkctrl:0000:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per2-clkctrl:0154:28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per2-clkctrl:0154:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per2-clkctrl:015c:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per2-clkctrl:018c:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per2-clkctrl:016c:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) DT_CLK(NULL, "mmc2_clk32k", "l3init-clkctrl:0010:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) DT_CLK(NULL, "mmc2_fclk_div", "l3init-clkctrl:0010:25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) DT_CLK(NULL, "mmc3_clk32k", "l4per-clkctrl:00f8:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) DT_CLK(NULL, "mmc3_gfclk_div", "l4per-clkctrl:00f8:25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) DT_CLK(NULL, "mmc4_clk32k", "l4per-clkctrl:0100:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) DT_CLK(NULL, "mmc4_gfclk_div", "l4per-clkctrl:0100:25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) DT_CLK(NULL, "optfclk_pciephy1_32khz", "pcie-clkctrl:0000:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) DT_CLK(NULL, "optfclk_pciephy1_clk", "pcie-clkctrl:0000:9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) DT_CLK(NULL, "optfclk_pciephy1_div_clk", "pcie-clkctrl:0000:10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) DT_CLK(NULL, "optfclk_pciephy2_32khz", "pcie-clkctrl:0008:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) DT_CLK(NULL, "optfclk_pciephy2_clk", "pcie-clkctrl:0008:9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) DT_CLK(NULL, "optfclk_pciephy2_div_clk", "pcie-clkctrl:0008:10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) DT_CLK(NULL, "qspi_gfclk_div", "l4per2-clkctrl:012c:25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init-clkctrl:00d0:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init-clkctrl:0020:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) { .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) int __init dra7xx_dt_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct clk *dpll_ck, *hdcp_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ti_dt_clocks_register(dra7xx_compat_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ti_dt_clocks_register(dra7xx_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) omap2_clk_disable_autoidle_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ti_clk_add_aliases();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) pr_err("%s: failed to configure USB DPLL!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) rc = clk_prepare_enable(hdcp_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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