^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DRA7 Clock init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Tero Kristo (t-kristo@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/dra7.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DRA7_DPLL_GMAC_DEFFREQ 1000000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DRA7_DPLL_USB_DEFFREQ 960000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) "per_abe_x1_gfclk2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) "video1_clk2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) "video2_clk2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) "hdmi_clk2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "abe_24m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "abe_sys_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) "func_24m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) "atl_clkin3_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "atl_clkin2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "atl_clkin1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "atl_clkin0_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "sys_clkin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "ref_clkin0_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "ref_clkin1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "ref_clkin2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "ref_clkin3_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "mlb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "mlbp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "timer_sys_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "sys_32k_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "sys_clkin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "ref_clkin0_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "ref_clkin1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "ref_clkin2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "ref_clkin3_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "abe_giclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "video1_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "video2_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "hdmi_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "clkoutmux0_clk_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "func_48m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "dpll_per_m2x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "sys_32k_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "video1_clkin_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "video2_clkin_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "hdmi_clkin_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "l3_iclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "dpll_abe_m2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "atl_cm:clk:0000:24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const char * const dra7_dss_dss_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "dpll_per_h12x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "func_48m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "hdmi_dpll_clk_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "sys_32k_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const char * const dra7_dss_video1_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "video1_dpll_clk_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const char * const dra7_dss_video2_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "video2_dpll_clk_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "func_128m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "dpll_per_m2x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "l3init_cm:clk:0008:24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .max_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "l3init_cm:clk:0010:24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .max_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "l3init_960m_gfclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const char * const dra7_sata_ref_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "sys_clkin1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "apll_pcie_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "optfclk_pciephy_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "dpll_gmac_h11x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "rmii_clk_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) "video1_clkin_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "video2_clkin_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "dpll_abe_m2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "hdmi_clkin_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "l3_iclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) "timer_sys_clk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "sys_32k_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "sys_clkin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "ref_clkin0_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) "ref_clkin1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "ref_clkin2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "ref_clkin3_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "abe_giclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "video1_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "video2_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) "hdmi_div_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "l4per_cm:clk:0120:24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .max_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "l4per_cm:clk:0128:24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .max_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) "func_128m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) "dpll_per_h13x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) "l4per_cm:clk:0138:24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .max_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) { DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) { DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) { DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) { DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) { DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) { DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) { DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) { DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) { DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) { DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) { DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) { DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) { DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) { DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) { DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) { DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) { DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) { DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) { DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) { DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) { DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) { DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) { DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) { DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) { DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) { DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) { DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) { DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) { DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) { DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) { DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) { DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) { DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) { DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) { DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) { DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) { DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) { DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) { DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) { DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) { DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) { DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) { DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) { DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) { DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) { DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) { DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) { DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div", "l4sec_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) { DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) { DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) { DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) { DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) { DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) { DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) { DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) "sys_clkin1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) "sys_clkin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) { DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) { DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) { DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) { DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) { DRA7_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) { DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) const struct omap_clkctrl_data dra7_clkctrl_compat_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) { 0x4a005320, dra7_mpu_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) { 0x4a005540, dra7_ipu_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) { 0x4a005740, dra7_rtc_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) { 0x4a008620, dra7_coreaon_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) { 0x4a008720, dra7_l3main1_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) { 0x4a008a20, dra7_dma_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) { 0x4a008b20, dra7_emif_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) { 0x4a008c00, dra7_atl_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) { 0x4a008d20, dra7_l4cfg_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) { 0x4a008e20, dra7_l3instr_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) { 0x4a009120, dra7_dss_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) { 0x4a009320, dra7_l3init_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) { 0x4a009700, dra7_l4per_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) { 0x4ae07820, dra7_wkupaon_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct ti_dt_clk dra7xx_compat_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) { .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags