^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP5 Clock init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Tero Kristo (t-kristo@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/clock/omap5.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OMAP5_DPLL_ABE_DEFFREQ 98304000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * states it must be at 960MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OMAP5_DPLL_USB_DEFFREQ 960000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h11x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const char * const omap5_aess_fclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) "abe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const struct omap_clkctrl_div_data omap5_aess_fclk_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .max_div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { 24, TI_CLK_DIVIDER, omap5_aess_fclk_parents, &omap5_aess_fclk_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const char * const omap5_dmic_gfclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "abe_cm:clk:0018:26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "pad_clks_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) "slimbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "abe_24m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "dss_syc_gfclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "func_24m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "abe_cm:clk:0028:26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "pad_clks_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "slimbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "abe_cm:clk:0030:26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "pad_clks_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "slimbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "abe_cm:clk:0038:26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "pad_clks_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "slimbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "dss_syc_gfclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "sys_32k_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "sys_clkin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "sys_32k_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const char * const omap5_gpio2_dbclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "sys_32k_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) omap_clkctrl_reg_data omap5_l4_secure_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { OMAP5_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { OMAP5_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { OMAP5_DES3DES_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { OMAP5_FPKA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { OMAP5_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { OMAP5_SHA2MD5_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { OMAP5_DMA_CRYPTO_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const struct omap_clkctrl_reg_data omap5_iva_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const char * const omap5_dss_dss_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "dpll_per_h12x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const char * const omap5_dss_48mhz_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "func_48m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const char * const omap5_dss_sys_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "dss_syc_gfclk_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const char * const omap5_gpu_core_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "dpll_core_h14x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "dpll_per_h14x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const char * const omap5_gpu_hyd_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "dpll_core_h14x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "dpll_per_h14x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const char * const omap5_gpu_sys_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "sys_clkin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct omap_clkctrl_div_data omap5_gpu_sys_clk_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .max_div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { 26, TI_CLK_DIVIDER, omap5_gpu_sys_clk_parents, &omap5_gpu_sys_clk_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) "func_128m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) "dpll_per_m2x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const char * const omap5_mmc1_fclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "l3init_cm:clk:0008:24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .max_div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const char * const omap5_mmc2_fclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) "l3init_cm:clk:0010:24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .max_div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) "l3init_60m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) "dpll_usb_m2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "l3init_cm:clk:0038:24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) "l3init_cm:clk:0038:25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "l3init_60m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) "xclk60mhsp1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) "l3init_60m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "xclk60mhsp2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) { 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) { 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) { 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) { 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) { 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) { 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static const char * const omap5_sata_ref_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) "sys_clkin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) "dpll_usb_clkdcoldo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) { 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) { OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) { OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) { OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) { OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) { 0x4a004320, omap5_mpu_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) { 0x4a004420, omap5_dsp_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) { 0x4a004520, omap5_abe_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) { 0x4a008720, omap5_l3main1_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) { 0x4a008820, omap5_l3main2_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) { 0x4a008920, omap5_ipu_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) { 0x4a008a20, omap5_dma_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) { 0x4a008b20, omap5_emif_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) { 0x4a008d20, omap5_l4cfg_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { 0x4a008e20, omap5_l3instr_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) { 0x4a009020, omap5_l4per_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { 0x4a0091a0, omap5_l4_secure_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { 0x4a009220, omap5_iva_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) { 0x4a009420, omap5_dss_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) { 0x4a009520, omap5_gpu_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) { 0x4a009620, omap5_l3init_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { 0x4ae07920, omap5_wkupaon_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static struct ti_dt_clk omap54xx_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int __init omap5xxx_dt_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ti_dt_clocks_register(omap54xx_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) omap2_clk_disable_autoidle_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ti_clk_add_aliases();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) pr_err("%s: failed to configure ABE DPLL!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) pr_err("%s: failed to configure USB DPLL!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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