^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP4 Clock init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Tero Kristo (t-kristo@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/omap4.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * half of this value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OMAP4_DPLL_ABE_DEFFREQ 98304000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * locked frequency for the USB DPLL is 960MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP4_DPLL_USB_DEFFREQ 960000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct omap_clkctrl_reg_data omap4_mpuss_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { OMAP4_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const struct omap_clkctrl_reg_data omap4_tesla_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { OMAP4_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_m4x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const char * const omap4_aess_fclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "abe_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const struct omap_clkctrl_div_data omap4_aess_fclk_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .max_div = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { 24, TI_CLK_DIVIDER, omap4_aess_fclk_parents, &omap4_aess_fclk_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "abe_cm:clk:0018:26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "pad_clks_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "slimbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const char * const omap4_dmic_sync_mux_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "abe_24m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "syc_clk_div_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "func_24m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { 24, TI_CLK_MUX, omap4_func_dmic_abe_gfclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "abe_cm:clk:0020:26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "pad_clks_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "slimbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { 24, TI_CLK_MUX, omap4_func_mcasp_abe_gfclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "abe_cm:clk:0028:26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "pad_clks_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "slimbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { 24, TI_CLK_MUX, omap4_func_mcbsp1_gfclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "abe_cm:clk:0030:26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "pad_clks_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "slimbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { 24, TI_CLK_MUX, omap4_func_mcbsp2_gfclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "abe_cm:clk:0038:26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "pad_clks_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "slimbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct omap_clkctrl_bit_data omap4_mcbsp3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { 24, TI_CLK_MUX, omap4_func_mcbsp3_gfclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const char * const omap4_slimbus1_fclk_0_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "abe_24m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const char * const omap4_slimbus1_fclk_1_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "func_24m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const char * const omap4_slimbus1_fclk_2_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "pad_clks_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const char * const omap4_slimbus1_slimbus_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "slimbus_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct omap_clkctrl_bit_data omap4_slimbus1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { 8, TI_CLK_GATE, omap4_slimbus1_fclk_0_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { 9, TI_CLK_GATE, omap4_slimbus1_fclk_1_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { 10, TI_CLK_GATE, omap4_slimbus1_fclk_2_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { 11, TI_CLK_GATE, omap4_slimbus1_slimbus_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const char * const omap4_timer5_sync_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "syc_clk_div_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "sys_32k_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct omap_clkctrl_bit_data omap4_timer5_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct omap_clkctrl_bit_data omap4_timer6_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct omap_clkctrl_bit_data omap4_timer7_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe_cm:clk:0020:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0040:8" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct omap_clkctrl_reg_data omap4_l4_ao_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { OMAP4_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { OMAP4_SMARTREFLEX_IVA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { OMAP4_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct omap_clkctrl_reg_data omap4_l3_1_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { OMAP4_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const struct omap_clkctrl_reg_data omap4_l3_2_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { OMAP4_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { OMAP4_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { OMAP4_OCMC_RAM_CLKCTRL, NULL, 0, "l3_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const struct omap_clkctrl_reg_data omap4_ducati_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { OMAP4_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "ducati_clk_mux_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct omap_clkctrl_reg_data omap4_l3_dma_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { OMAP4_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct omap_clkctrl_reg_data omap4_l3_emif_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { OMAP4_DMM_CLKCTRL, NULL, 0, "l3_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { OMAP4_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { OMAP4_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const struct omap_clkctrl_reg_data omap4_d2d_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { OMAP4_C2C_CLKCTRL, NULL, 0, "div_core_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const struct omap_clkctrl_reg_data omap4_l4_cfg_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { OMAP4_L4_CFG_CLKCTRL, NULL, 0, "l4_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { OMAP4_SPINLOCK_CLKCTRL, NULL, 0, "l4_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { OMAP4_MAILBOX_CLKCTRL, NULL, 0, "l4_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const struct omap_clkctrl_reg_data omap4_l3_instr_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { OMAP4_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { OMAP4_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { OMAP4_OCP_WP_NOC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const struct omap_clkctrl_reg_data omap4_ivahd_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { OMAP4_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { OMAP4_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const char * const omap4_iss_ctrlclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "func_96m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct omap_clkctrl_bit_data omap4_iss_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { 8, TI_CLK_GATE, omap4_iss_ctrlclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const char * const omap4_fdif_fck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "dpll_per_m4x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const struct omap_clkctrl_div_data omap4_fdif_fck_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .max_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { 24, TI_CLK_DIVIDER, omap4_fdif_fck_parents, &omap4_fdif_fck_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss_cm:clk:0008:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const char * const omap4_dss_dss_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "dpll_per_m5x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const char * const omap4_dss_48mhz_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "func_48mc_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const char * const omap4_dss_sys_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "syc_clk_div_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const char * const omap4_dss_tv_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "extalt_clkin_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { 8, TI_CLK_GATE, omap4_dss_dss_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { 9, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { 10, TI_CLK_GATE, omap4_dss_sys_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 11, TI_CLK_GATE, omap4_dss_tv_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3_dss_cm:clk:0000:8" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const char * const omap4_sgx_clk_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "dpll_core_m7x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "dpll_per_m7x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { 24, TI_CLK_MUX, omap4_sgx_clk_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3_gfx_cm:clk:0000:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const char * const omap4_hsmmc1_fclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "func_64m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "func_96m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct omap_clkctrl_bit_data omap4_mmc1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct omap_clkctrl_bit_data omap4_mmc2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const char * const omap4_hsi_fck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "dpll_per_m2x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const struct omap_clkctrl_div_data omap4_hsi_fck_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .max_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { 24, TI_CLK_DIVIDER, omap4_hsi_fck_parents, &omap4_hsi_fck_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "l3_init_cm:clk:0038:24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "l3_init_cm:clk:0038:25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const char * const omap4_usb_host_hs_utmi_p3_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) "init_60m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const char * const omap4_usb_host_hs_hsic480m_p1_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "dpll_usb_m2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const char * const omap4_utmi_p1_gfclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "init_60m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "xclk60mhsp1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const char * const omap4_utmi_p2_gfclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) "init_60m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "xclk60mhsp2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p1_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) { 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p2_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { 11, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { 12, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { 13, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { 14, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { 15, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { 24, TI_CLK_MUX, omap4_utmi_p1_gfclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { 25, TI_CLK_MUX, omap4_utmi_p2_gfclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) "l3_init_cm:clk:0040:24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const char * const omap4_otg_60m_gfclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) "utmi_phy_clkout_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "xclk60motg_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const struct omap_clkctrl_bit_data omap4_usb_otg_hs_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) { 8, TI_CLK_GATE, omap4_usb_otg_hs_xclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { 24, TI_CLK_MUX, omap4_otg_60m_gfclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const struct omap_clkctrl_bit_data omap4_usb_tll_hs_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) { 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) { 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const char * const omap4_ocp2scp_usb_phy_phy_48m_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "func_48m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) { 8, TI_CLK_GATE, omap4_ocp2scp_usb_phy_phy_48m_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0008:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0010:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:0018:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) { OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) { OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) { OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:00c0:8" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static const char * const omap4_cm2_dm10_mux_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "sys_clkin_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "sys_32k_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static const struct omap_clkctrl_bit_data omap4_timer10_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static const struct omap_clkctrl_bit_data omap4_timer11_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const struct omap_clkctrl_bit_data omap4_timer2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static const struct omap_clkctrl_bit_data omap4_timer3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const struct omap_clkctrl_bit_data omap4_timer4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static const struct omap_clkctrl_bit_data omap4_timer9_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const char * const omap4_gpio2_dbclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) "sys_32k_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static const struct omap_clkctrl_bit_data omap4_gpio2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const struct omap_clkctrl_bit_data omap4_gpio3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const struct omap_clkctrl_bit_data omap4_gpio4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static const struct omap_clkctrl_bit_data omap4_gpio5_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) "l4_per_cm:clk:00c0:26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) "pad_clks_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static const char * const omap4_mcbsp4_sync_mux_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) "func_96m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) "per_abe_nc_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const struct omap_clkctrl_bit_data omap4_mcbsp4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) { 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) { 26, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static const char * const omap4_slimbus2_fclk_0_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) "func_24mc_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static const char * const omap4_slimbus2_fclk_1_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) "per_abe_24m_fclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const char * const omap4_slimbus2_slimbus_clk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "pad_slimbus_core_clks_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) { 8, TI_CLK_GATE, omap4_slimbus2_fclk_0_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) { 9, TI_CLK_GATE, omap4_slimbus2_fclk_1_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) { 10, TI_CLK_GATE, omap4_slimbus2_slimbus_clk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0008:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0010:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0018:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0020:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0028:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0030:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) { OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) { OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) { OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) { OMAP4_GPIO4_CLKCTRL, omap4_gpio4_bit_data, CLKF_HW_SUP, "l4_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) { OMAP4_GPIO5_CLKCTRL, omap4_gpio5_bit_data, CLKF_HW_SUP, "l4_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) { OMAP4_GPIO6_CLKCTRL, omap4_gpio6_bit_data, CLKF_HW_SUP, "l4_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) { OMAP4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) { OMAP4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) { OMAP4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) { OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) { OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) { OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:00c0:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) { OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) { OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) { OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) { OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) { OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0118:8" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) { OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) { OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) { OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { OMAP4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) { OMAP4_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static const struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) omap_clkctrl_reg_data omap4_l4_secure_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) { OMAP4_AES1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) { OMAP4_AES2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) { OMAP4_DES3DES_CLKCTRL, NULL, CLKF_SW_SUP, "l4_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) { OMAP4_PKA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) { OMAP4_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) { OMAP4_SHA2MD5_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) { OMAP4_CRYPTODMA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static const struct omap_clkctrl_bit_data omap4_gpio1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static const struct omap_clkctrl_bit_data omap4_timer1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) { OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0020:24" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) { OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) { OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) "sys_clkin_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) "dpll_core_m6x2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) "tie_low_clock_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) "emu_sys_cm:clk:0000:22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static const int omap4_trace_clk_div_div_ck_divs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .dividers = omap4_trace_clk_div_div_ck_divs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static const char * const omap4_stm_clk_div_ck_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) "emu_sys_cm:clk:0000:20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static const struct omap_clkctrl_div_data omap4_stm_clk_div_ck_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .max_div = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .flags = CLK_DIVIDER_POWER_OF_TWO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static const struct omap_clkctrl_bit_data omap4_debugss_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) { 20, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) { 22, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) { 24, TI_CLK_DIVIDER, omap4_trace_clk_div_div_ck_parents, &omap4_trace_clk_div_div_ck_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) { 27, TI_CLK_DIVIDER, omap4_stm_clk_div_ck_parents, &omap4_stm_clk_div_ck_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static const struct omap_clkctrl_reg_data omap4_emu_sys_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) { OMAP4_DEBUGSS_CLKCTRL, omap4_debugss_bit_data, 0, "trace_clk_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) { 0x4a004320, omap4_mpuss_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) { 0x4a004420, omap4_tesla_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) { 0x4a004520, omap4_abe_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) { 0x4a008620, omap4_l4_ao_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) { 0x4a008720, omap4_l3_1_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) { 0x4a008820, omap4_l3_2_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) { 0x4a008920, omap4_ducati_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) { 0x4a008a20, omap4_l3_dma_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) { 0x4a008b20, omap4_l3_emif_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) { 0x4a008c20, omap4_d2d_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) { 0x4a008d20, omap4_l4_cfg_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) { 0x4a008e20, omap4_l3_instr_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) { 0x4a008f20, omap4_ivahd_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) { 0x4a009020, omap4_iss_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) { 0x4a009120, omap4_l3_dss_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) { 0x4a009220, omap4_l3_gfx_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) { 0x4a009320, omap4_l3_init_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) { 0x4a009420, omap4_l4_per_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) { 0x4a0095a0, omap4_l4_secure_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) { 0x4a307820, omap4_l4_wkup_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) { 0x4a307a20, omap4_emu_sys_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static struct ti_dt_clk omap44xx_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * XXX: All the clock aliases below are only needed for legacy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * hwmod support. Once hwmod is removed, these can be removed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * also.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) DT_CLK(NULL, "aess_fclk", "abe_cm:0008:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) DT_CLK(NULL, "cm2_dm10_mux", "l4_per_cm:0008:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) DT_CLK(NULL, "cm2_dm11_mux", "l4_per_cm:0010:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) DT_CLK(NULL, "cm2_dm2_mux", "l4_per_cm:0018:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) DT_CLK(NULL, "cm2_dm3_mux", "l4_per_cm:0020:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) DT_CLK(NULL, "cm2_dm4_mux", "l4_per_cm:0028:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) DT_CLK(NULL, "cm2_dm9_mux", "l4_per_cm:0030:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) DT_CLK(NULL, "dmt1_clk_mux", "l4_wkup_cm:0020:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) DT_CLK(NULL, "dss_48mhz_clk", "l3_dss_cm:0000:9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) DT_CLK(NULL, "dss_dss_clk", "l3_dss_cm:0000:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) DT_CLK(NULL, "dss_sys_clk", "l3_dss_cm:0000:10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) DT_CLK(NULL, "dss_tv_clk", "l3_dss_cm:0000:11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) DT_CLK(NULL, "fdif_fck", "iss_cm:0008:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) DT_CLK(NULL, "func_dmic_abe_gfclk", "abe_cm:0018:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe_cm:0020:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) DT_CLK(NULL, "func_mcbsp1_gfclk", "abe_cm:0028:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) DT_CLK(NULL, "func_mcbsp2_gfclk", "abe_cm:0030:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) DT_CLK(NULL, "func_mcbsp3_gfclk", "abe_cm:0038:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) DT_CLK(NULL, "gpio1_dbclk", "l4_wkup_cm:0018:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0040:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0048:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0050:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0058:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) DT_CLK(NULL, "gpio6_dbclk", "l4_per_cm:0060:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) DT_CLK(NULL, "hsi_fck", "l3_init_cm:0018:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) DT_CLK(NULL, "hsmmc1_fclk", "l3_init_cm:0008:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) DT_CLK(NULL, "hsmmc2_fclk", "l3_init_cm:0010:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) DT_CLK(NULL, "iss_ctrlclk", "iss_cm:0000:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) DT_CLK(NULL, "mcasp_sync_mux_ck", "abe_cm:0020:26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4_per_cm:00c0:26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3_init_cm:00c0:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) DT_CLK(NULL, "otg_60m_gfclk", "l3_init_cm:0040:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) DT_CLK(NULL, "per_mcbsp4_gfclk", "l4_per_cm:00c0:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu_sys_cm:0000:20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu_sys_cm:0000:22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) DT_CLK(NULL, "sgx_clk_mux", "l3_gfx_cm:0000:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) DT_CLK(NULL, "slimbus1_fclk_0", "abe_cm:0040:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) DT_CLK(NULL, "slimbus1_fclk_1", "abe_cm:0040:9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) DT_CLK(NULL, "slimbus1_fclk_2", "abe_cm:0040:10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) DT_CLK(NULL, "slimbus1_slimbus_clk", "abe_cm:0040:11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) DT_CLK(NULL, "slimbus2_fclk_0", "l4_per_cm:0118:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) DT_CLK(NULL, "slimbus2_fclk_1", "l4_per_cm:0118:9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) DT_CLK(NULL, "slimbus2_slimbus_clk", "l4_per_cm:0118:10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) DT_CLK(NULL, "stm_clk_div_ck", "emu_sys_cm:0000:27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) DT_CLK(NULL, "timer5_sync_mux", "abe_cm:0048:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) DT_CLK(NULL, "timer6_sync_mux", "abe_cm:0050:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) DT_CLK(NULL, "timer7_sync_mux", "abe_cm:0058:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) DT_CLK(NULL, "timer8_sync_mux", "abe_cm:0060:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) DT_CLK(NULL, "trace_clk_div_div_ck", "emu_sys_cm:0000:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) DT_CLK(NULL, "usb_host_hs_func48mclk", "l3_init_cm:0038:15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3_init_cm:0038:13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3_init_cm:0038:14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3_init_cm:0038:11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3_init_cm:0038:12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3_init_cm:0038:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3_init_cm:0038:9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init_cm:0038:10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) DT_CLK(NULL, "usb_otg_hs_xclk", "l3_init_cm:0040:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3_init_cm:0048:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3_init_cm:0048:9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3_init_cm:0048:10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) DT_CLK(NULL, "utmi_p1_gfclk", "l3_init_cm:0038:24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) DT_CLK(NULL, "utmi_p2_gfclk", "l3_init_cm:0038:25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) { .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) int __init omap4xxx_dt_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ti_dt_clocks_register(omap44xx_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) omap2_clk_disable_autoidle_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ti_clk_add_aliases();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * Lock USB DPLL on OMAP4 devices so that the L3INIT power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * domain can transition to retention state when not in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) pr_err("%s: failed to configure USB DPLL!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * state when turning the ABE clock domain. Workaround this by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * locking the ABE DPLL on boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * Lock the ABE DPLL in any case to avoid issues with audio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) pr_err("%s: failed to configure ABE DPLL!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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