^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * AM43XX Clock init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 Texas Instruments, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Tero Kristo (t-kristo@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <dt-bindings/clock/am4.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const struct omap_clkctrl_reg_data am4_l3s_tsc_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { AM4_L3S_TSC_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static const char * const am4_synctimer_32kclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) "mux_synctimer32k_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const struct omap_clkctrl_reg_data am4_l4_wkup_aon_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sys_clkin_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4-wkup-aon-clkctrl:0008:8" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const char * const am4_gpio0_dbclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "gpio0_dbclk_mux_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { AM4_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { AM4_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { AM4_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { AM4_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { AM4_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { AM4_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { AM4_L4_WKUP_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { AM4_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { AM4_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ick" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct omap_clkctrl_reg_data am4_l3_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { AM4_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { AM4_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { AM4_L3_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { AM4_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { AM4_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { AM4_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { AM4_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { AM4_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { AM4_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { AM4_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { AM4_L3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "dpll_per_clkdcoldo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const struct omap_clkctrl_reg_data am4_l3s_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { AM4_L3S_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { AM4_L3S_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { AM4_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { AM4_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { AM4_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { AM4_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { AM4_L3S_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { AM4_L3S_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { AM4_L3S_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct omap_clkctrl_reg_data am4_pruss_ocp_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { AM4_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "pruss_ocp_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const char * const am4_gpio1_dbclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "clkdiv32k_ick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct omap_clkctrl_reg_data am4_l4ls_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { AM4_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { AM4_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { AM4_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { AM4_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { AM4_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { AM4_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { AM4_L4LS_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { AM4_L4LS_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { AM4_L4LS_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { AM4_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { AM4_L4LS_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { AM4_L4LS_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { AM4_L4LS_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { AM4_L4LS_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { AM4_L4LS_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { AM4_L4LS_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { AM4_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { AM4_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { AM4_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { AM4_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { AM4_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { AM4_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { AM4_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { AM4_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { AM4_L4LS_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { AM4_L4LS_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { AM4_L4LS_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { AM4_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { AM4_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { AM4_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { AM4_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { AM4_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { AM4_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { AM4_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { AM4_L4LS_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { AM4_L4LS_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { AM4_L4LS_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { AM4_L4LS_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { AM4_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { AM4_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { AM4_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { AM4_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { AM4_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { AM4_L4LS_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { AM4_L4LS_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const struct omap_clkctrl_reg_data am4_emif_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { AM4_EMIF_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const struct omap_clkctrl_reg_data am4_dss_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { AM4_DSS_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct omap_clkctrl_reg_data am4_cpsw_125mhz_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) const struct omap_clkctrl_data am4_clkctrl_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { 0x44df2920, am4_l3s_tsc_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { 0x44df2a20, am4_l4_wkup_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { 0x44df8320, am4_mpu_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { 0x44df8420, am4_gfx_l3_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { 0x44df8520, am4_l4_rtc_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 0x44df8820, am4_l3_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { 0x44df8868, am4_l3s_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { 0x44df8c20, am4_l4ls_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { 0x44df8f20, am4_emif_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { 0x44df9220, am4_dss_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) const struct omap_clkctrl_data am438x_clkctrl_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { 0x44df2920, am4_l3s_tsc_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { 0x44df2a20, am4_l4_wkup_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { 0x44df8320, am4_mpu_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { 0x44df8420, am4_gfx_l3_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { 0x44df8820, am4_l3_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { 0x44df8868, am4_l3s_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { 0x44df8c20, am4_l4ls_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { 0x44df8f20, am4_emif_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { 0x44df9220, am4_dss_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct ti_dt_clk am43xx_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0148:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0058:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0060:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:0068:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) DT_CLK(NULL, "gpio4_dbclk", "l4ls-clkctrl:0070:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) DT_CLK(NULL, "gpio5_dbclk", "l4ls-clkctrl:0078:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) DT_CLK(NULL, "synctimer_32kclk", "l4-wkup-aon-clkctrl:0008:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l3s-clkctrl:01f8:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3s-clkctrl:0200:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int __init am43xx_dt_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct clk *clk1, *clk2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ti_dt_clocks_register(am43xx_compat_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ti_dt_clocks_register(am43xx_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) omap2_clk_disable_autoidle_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ti_clk_add_aliases();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * cpsw_cpts_rft_clk has got the choice of 3 clocksources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * By default dpll_core_m4_ck is selected, witn this as clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * source the CPTS doesnot work properly. It gives clockcheck errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * while running PTP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * clockcheck: clock jumped backward or running slower than expected!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * By selecting dpll_core_m5_ck as the clocksource fixes this issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * In AM335x dpll_core_m5_ck is the default clocksource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) clk2 = clk_get_sys(NULL, "dpll_core_m5_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) clk_set_parent(clk1, clk2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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