Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * AM43XX Clock init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2013 Texas Instruments, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *     Tero Kristo (t-kristo@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <dt-bindings/clock/am4.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static const char * const am4_synctimer_32kclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	"mux_synctimer32k_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	{ 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static const char * const am4_gpio0_dbclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	"gpio0_dbclk_mux_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	{ 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	{ AM4_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck", "l3s_tsc_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	{ AM4_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	{ AM4_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "sys_clkin_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	{ AM4_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0210:8" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	{ AM4_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck", "l4_wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	{ AM4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck", "l4_wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	{ AM4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	{ AM4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	{ AM4_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck", "l4_wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	{ AM4_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck", "l4_wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	{ AM4_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{ AM4_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	{ AM4_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	{ AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	{ AM4_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	"dpll_per_clkdcoldo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	{ 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{ 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static const char * const am4_gpio1_dbclk_parents[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	"clkdiv32k_ick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct omap_clkctrl_reg_data am4_l4_per_clkctrl_regs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{ AM4_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	{ AM4_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	{ AM4_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	{ AM4_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{ AM4_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{ AM4_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	{ AM4_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	{ AM4_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{ AM4_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	{ AM4_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	{ AM4_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	{ AM4_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	{ AM4_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	{ AM4_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	{ AM4_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	{ AM4_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	{ AM4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	{ AM4_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	{ AM4_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	{ AM4_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	{ AM4_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	{ AM4_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	{ AM4_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	{ AM4_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	{ AM4_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	{ AM4_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	{ AM4_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	{ AM4_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	{ AM4_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{ AM4_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{ AM4_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	{ AM4_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	{ AM4_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	{ AM4_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	{ AM4_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	{ AM4_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	{ AM4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	{ AM4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	{ AM4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	{ AM4_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	{ AM4_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	{ AM4_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	{ AM4_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	{ AM4_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	{ AM4_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	{ AM4_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	{ AM4_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	{ AM4_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	{ AM4_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	{ AM4_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	{ AM4_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	{ AM4_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	{ AM4_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	{ AM4_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	{ AM4_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	{ AM4_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	{ AM4_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	{ AM4_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	{ AM4_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	{ AM4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	{ AM4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	{ AM4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	{ AM4_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	{ AM4_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	{ AM4_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	{ AM4_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	{ AM4_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck", "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	{ AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk", "dss_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	{ AM4_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) const struct omap_clkctrl_data am4_clkctrl_compat_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	{ 0x44df2820, am4_l4_wkup_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	{ 0x44df8320, am4_mpu_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	{ 0x44df8420, am4_gfx_l3_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	{ 0x44df8520, am4_l4_rtc_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	{ 0x44df8820, am4_l4_per_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) const struct omap_clkctrl_data am438x_clkctrl_compat_data[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	{ 0x44df2820, am4_l4_wkup_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	{ 0x44df8320, am4_mpu_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	{ 0x44df8420, am4_gfx_l3_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	{ 0x44df8820, am4_l4_per_clkctrl_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	{ 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct ti_dt_clk am43xx_compat_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0348:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0458:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0460:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0468:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0470:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0478:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	DT_CLK(NULL, "synctimer_32kclk", "l4_wkup_cm:0210:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l4_per_cm:0240:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l4_per_cm:0248:8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	{ .node_name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };